Hi. This is going to be a video about how engineering minds can often think alike on projects even though they're on opposite sides of the planet in different worlds before the Internet joined us all together. So let's take a look at some old magazine projects and I've done this one before. Uh, back in October 1996, I got my Uh.

32 Channel 40 Megahertz Logic Analyzer Pc based logic analyzer project that published and here's the original prototype here. I'll uh, link in a video up here and down below if you haven't seen it and this is where I go over the design of this thing. Uh, talking about the whole history of that and uh, looking at my original, uh, drawings and things like that for it. Now I can't remember the exact uh history behind this, but I believe that uh, somebody like ages ago I've had this forever told me about this Elector Electronics uh magazine from the Uk and it's from 1996 as well.

And they published a logic analyzer which is near identical, uh, to my design and they thought, oh, they had copied it or something like that. But as it turns out, um, Elector Electronics actually published this design. Uh, you can see May 1996 actually published it before mine. Aha, does that mean Dave, you copied their design? Oh well, no, we'll take a look at it.

We couldn't actually get this magazine in Australia way back in 1996. I never recall, ever seen. I don't think I had ever actually heard of it back then, because you've got to remember, right? 1996? Well okay, the World Wide Web had just started, but practically you know we still lived in like the isolated world. Okay, it's not the Internet that we take for granted these days.

So pretty much if you didn't see a magazine in your news agent or you weren't told about it by somebody else, you didn't find it in your school library or something like that university library, then well, you just wouldn't know about these magazines. So yeah, I had no clue about this, so I can't remember if somebody sent me this magazine or I acquired it so that I could check it out after they, um, said hey, you know you should check this out, see if they copied your design. So anyway, had this for a long time, so I thought we'd just take a look at the differences and the similarities between these two designs and and why two designers on opposite sides of the planet pretty much came to the same conclusion as far as designing a Pc based logic analyzer in 1995 1996. So just to prove of course that mine does, actually, uh, predate this design even though it was October 1996.

If you don't know, getting a project published in a magazine can take many months lead time, they need to allocate a certain number of pages certain slot. And because my design was a large project, I think this one's eight pages. The next issue is eight pages or something. Uh, and it was spread over two issues.

You know they need to sort of like they've got their own designs in the pipeline and things like that so you get slotted in so I can't remember when I submitted this. but if we have a look at my original prototype here, here we go. I even dated it isn't that handy the 25th of February 96 and as I've gone through in a previous video in some detail, I'm sure my original, uh, like lab notebook uh, sketches of the original uh design and the timing diagrams and things like that. look at that.

I've done a video on doing your own timing diagrams as you can see the date uh, 17th of the 8th, 95, 25th of the 8th, 95, 28th of the 8th 95. So yeah, late 95, but it didn't get published until practically a year later. And yes, I was pretty bummed that my, uh, big project didn't make the front cover. They had a bloody Sony's new mini disc and and this uh, Pc sleuth card got the front cover.

I remember, you know, I was only young. I was getting a bit miffed. Anyway, let's check it out, but I was kind of chuffed when I got uh, the like featured in the side column here and there it goes. Page 90 Pc based logic analyzer, Part One, design background and how it works.

All right. this is going to be easier if we just go to the Pdf and thankfully, you can actually download all of the Archives of Electronics Australia and other magazines on Archive.org Now you can also get a electoral magazine as well. Unfortunately, they don't actually have the 1996 issue. It jumps from 89 to like 2004, so that's a bummer.

Anyway, we've scanned it in. Uh, so we can go to the videotape and like it's They're really good quality scans too. So absolutely Fanta Moffat's madhouse. Sadly, he's not with us anymore.

Tom Moffatt. But uh. anyway. yeah, let's go to the Pdf.

Yes, for all you floating Dave Head aficionados, we'll just randomly move Dave Head. I know some people want it down the bottom, but I think the majority want Dave floating. Dave Head somewhere to move around. anyway.

Rod Irving Electronics. Who? Who remembers Rod Irving? Anyway, here we go. Um, the Pc Based Logic Analyzer. Part A One: Uh, David Bulfoni uh, is a friend of mine.

Uh, we just like worked on designs back then. He didn't really have much if anything to do with this project, but we sort of like were discussing stuff at the time, so I thought I'd uh, include his name in there. Just to you know, give him a bit of a leg up in the industry because remember, I've mentioned, one of the best things you can do is to actually get published in the magazines and that looks great on your resumes. Even today, it's still a thing.

It looks very impressive, especially to the Hr droids. anyway. so let's have a look at some of the similarities between the designs. Now mine's a 32 channel job.

Ttl Cmos compatibility fully. Uh, it's a Pc based internal logic analyzer. Uh, it goes up to 40 megahertz external, Uh, 20 megahertz. It's got latch, trigger word masking.

It's got full masking for all 32 channels and optional glitch capture. I don't actually remember what that's about. I have to read my own article. Anyway, I'll link it in.

uh, down below if you want to have a squeeze at the full thing to the electoral design are designed by El Lamesh. I believe that's uh, Laurent Lamesh. So let's have a look at the specs down here. now.

This one actually had uh, selectable channels anywhere from 16 to 64. mine was just a fixed 32. so if we have a look at the base level board I think it's uh, like it could be like 16 and then you can like plug on expansion boards. Now input level: Ttl.

I think this is incorrect and we'll have a look at why later. But anyway. um, this one I didn't put in my specs but this one only has 4k. Uh, sample memory.

Mine's got 32k and we'll go into some of the differences that makes in terms of the design of the main control chip. Uh, trigger point: It's in the center, internal or external. This design got 50 megahertz. I only pushed mine to 40.

I can't remember why I pushed it to 40. I don't know if it was capable of 50 or not. I don't uh recall. But anyway, um, they claim uh, external is also 50 I believe like mine was uh, lower spec for external so I don't remember why I actually uh did that anyway.

Oh, we won't go into deep technical details and maybe I covered that in my previous video. I don't know. It's like an hour long. I'm not gonna re-watch it anyway.

Uh, once again, it's got like programmable trigger stuff and things like that. and it's a Pc printer port just like mine. Um, a bit. Of course The form factories are significantly different to my mind, was built into one of those pack tech cases.

This one was like more compact and had multiple Uh boards now. But the huge difference between the designs is that this one used double-sided plated through boards. Mine was a specific single-sided design and that's a huge difference. I made the conscious choice and because back then you got to remember Pcb design was like you can't get your double sided plated through board for five bucks like you can these days.

It was minimum of hundreds of dollars tooling fee just to get the tooling fee let alone the actual boards. And typically you wouldn't share project panels. Uh, you had to buy the entire panel like the full size panel. So you know it wasn't uncommon to pay like 500 or 800 dollars, especially here in Australia to get a board like a double-sided plate through board.

uh, prototype manufactured. You take it for granted that you get it for, you know, five, ten bucks delivered these days or whatever. But for five boards, which is just nuts. But back then it was a big deal.

A lot of people, including myself, still manufactured their own boards. I manufactured my uh, prototype board uh, that you saw before, so I manufactured a couple of versions of that. So really, one of the goals of publishing a magazine project is so that you're effectively open sourcing the design so that you provide the Pcb layouts in like one to one in the magazine. Or you could download it from the Early Electronics Australia bulletin board.

At the time you know you dialed into the Bbs with your 300 board or 1200 board modem that was screaming and you would download the Pcb files. Or you simply scanned it from the magazine and with the photocopier and you manufactured the overlay yourself and you etched, you know, exposed and etched and drilled your own board. That was very common. So one of my goals was to make it so that anyone could manufacture this thing and you could download the programmable logic files.

as we'll see, you could download that from the bulletin board for free and things like that. But I did actually sell pre-programmed chips for this thing if you wanted that, but you didn't have to, it was all open. You could effectively just download it and build it yourself. So yeah, I had the target goal of single-sided board.

They obviously went. oh, this has got to be double-sided and you know that's it. Now one of the things that made these designs very similar, almost copied in quote marks is that they both used the Lattice Isp 1016 Lsi Isp Lsi 1016 programmable logic device from Lattice Semiconductor and it had uh, both designs actually had a control Uh, they had a control uh pld down here and then a like a channel pld over here which did the mask, uh, triggering and stuff like that. So both designs would like from that point of view identical.

So here's a look inside the control Lsi uh chip over here and you can see it's going to be. I'll compare it with mine, it's going to be more complicated and they've got the state diagram over here. I didn't do a state diagram for mine so that's interesting. but anyway, it's got uh, it looks like a pre and post trigger counters in here like this because you have to get a trigger point in the middle of your sample and you know you had to do a little bit of logic to actually do that to ensure you get 50 Uh, pre-sample 50 post sample because that's very common not only oscilloscopes, but also logic analyzers.

That's uh, the default 50 pre and post because when you trigger on something okay, you set your trigger point. but usually you often want to see what caused that trigger and then you want to see what happened after that trigger. Hence, why 50 percent are pre-post So that's why we've got looks like, uh, I'm not going to analyze this in depth, but that's why you got, uh, true trigger and then you've got trigger logic here. By the looks of it, it looks significantly more, uh, complicated than mine anyway.

Um, this is the oscillator input here. uh, this is the oscillator divider. you'll see, uh, in a minute that I do mine external, uh to the chip and I'll potentially explain why in a minute and preset down counters. And anyway, there you go that's internal to the logic control chip.

and then they've got the trigger chip down here and we'll compare the two trigger chips shortly. but very similar. and I think we'll see on my design here the overall uh, block diagram a little bit better than on their one. What we've got here is our inputs down here.

We've got our pull-up resistors here. We've got 74 Act five, seven fours here. I mention those in a minute. Then we've got the Uh Sram a six, two, two five six which was the uh, popular cash and popular.

relatively cheap and readily available uh, cash sram memory that was used in Pcs at the time. And does anyone remember the fake case scam? Whether you get either fake or blank uh chips and you'd pay these chips, you'd put them in and people think that their computer's faster. but it wasn't unless you really benchmarked it properly. Anyway, the fake case ram scam? That was, uh, great.

Anyway, Um, and then I've got two Isp Lsi 1016 logic devices here. Uh, one for each 16 Uh channels. They're the trigger chip and then one control Isp Lsi 1016 over there. Oops, It looks like my Pdf didn't insert the several pages from this.

Anyway, here's their overall block diagram here and it's very similar. Look at this. So here's their input connector over here. They used exactly the same 0.1 inch header as I did, because that was, of course, the obvious choice.

What what else would you use? Even today, you would still use a 0.1 inch header. That's what you still get on a lot of oscilloscopes these days. You'll get a 0.1 each header because it's just standard, industry proven easy, simple, cheap, and then you've got pull-up resistors exactly like I did and then 74 Ac 574. They used exactly the same chip here, but they used an Ac, not an Ac whereas I use the Act version and the Ac is a Cmos version.

Ac stands for advanced Cmos. That means it has Cmos compatible input levels, but if you get the Act version, that means the T stands for Ttl compatible logic threshold levels and there is a, you know, a significant difference there, so I don't understand. As I said, why in their specs down here, Get Dave. Head out of the way that they actually claim Ttl input level compatibility.

How can you claim that when you don't have Ttl compatible parts whereas I specifically use the Ttlr compatible part? So anyway, like in most cases, it's not a huge deal. So why did we both choose 74 Ac variant 574 chip? Because the 574 is your standard octal D-type flip-flop Um, it's just like the obvious choice. what else would you use Now, you could have potentially incorporated that inside the Pld device itself, but I don't believe it actually had the flexibility because it's only a Pld, a programmable logic device. It's not an Fpga which uses a more complex fabric inside with more flip-flop availability and stuff like that.

So I'm sure both of us would have, uh, investigated that. I don't recall precisely. It was like, come on, it's like 25 years ago. It's a long time ago I'm sure I would have investigated.

They're going. Oh, look, I don't have this. Pld doesn't have the input flexibility to actually, uh, do this. So we need an external latching chip because you've got to latch all of the data at the same time across all your channels.

So you want to do that with one synchronous clock? So you need an octal D type flip-flop or some sort of octal latch or something like that and you want eight? You want to minimize your number of chips. so you're going to choose an octal version which has a There are like other obscure 16 channel variants probably, but like you can't get them whereas you can go down to your local store. You know you could go down in your local tricky dicks. And you could buy a you know, a 74574.

but you know, the Ac variant you might have to get. They're a bit special anyway. So certainly yes, the Ac574 because has an enable. it has a clock input and it just latches all of the data.

So yes, you want that synchronous sampling Here it is. It's got the clock input down here, and then it just samples. All the channels are at exactly the same time and that's exactly what you want for both. uh, timing analysis mode and state analysis mode.

But there's basically two modes. every logic analyzer good one should have time in analysis mode which uses an internal clock and state analysis mode which uses an external clock. So in the case of state analysis, this external clock here could actually come from your circuit under test. So that's how you can synchronize the sampling of your input latches to your circuit under test.

And that might be vital as opposed to asynchronous sampling which uses an internal free running clock just latching this stuff in. So yeah, that was just the obvious choice. No surprises why we both chose an identical front end here and of course then we you would latch that directly in this case into the uh, the trigger pld which is this one? yeah, they actually call it trigger unit and the control unit. and my it looks like their main board only uses only has the one trigger unit where whereas I had two because mine was a 32 channel design on the one board and it just made sense to uh, separate the trigger unit from the control unit like this as well as there just simply wasn't the internal resources to do everything in one chip.

um, a Ua you didn't have the pin count uh to do it and b it didn't have the internal logic and I'm sure in my previous video I've shown that or explained that I had like 98 or near 100 utilization in in these devices. So my all the logic and stuff barely fitted. So from an architecture point of view, the front end and the triggering and control aspect of this these I you could essentially say they're like not identical designers, but you know they they're basically following the simmer approach and they're using the exact same programmable logic device. Why did we both choose like two engineers on the other side of the planet choose exactly the same Cpld to do the job? Well, They actually hint here in this article.

I didn't I don't know if I mentioned it in mine, I don't think so, but they hint here that further reading. There you go. the Isp starter kit in December 94. It looks like I haven't checked, but they obviously did an article featuring the Lattice Isp Lsi starter kit which you could buy for 99 us dollars.

It was about sold for about 150 Australian dollars here. and obviously I saw this ad in the Local Electronics Australia magazine at the time. I don't know if they ran an article on it or it's just an ad and I went whoa. Wow! You can do programmable logic for 150 bucks because you're going to remember this is like the mid 90s If you want to do Fpgas or Plds back then you like.

It was thousands of dollars and you had to be a big company or whatever like it was really difficult for like the hobbyist or the midnight engineer the one-man band to actually get into Fpgas It was seriously expensive business. The software tools alone cost thousands of dollars and the demo like starter kit boards and things like that, then another couple of hundred dollars again minimum and so it cost you thousands of dollars to get into programmable logic devices and or Fpgas because none of the free tools that we take uh for granted these days it cost serious money. So when lettuce came out and said look, we've got this isp Lsi starter kit for like 99 bucks. 150 bucks Aussie bucks Win a win at chicken dinner like we both obviously saw that ad and went and jumped on that and went wow this is great.

I have no idea I'm just buying this kit. What what can I use it for? Hmm Logic analyzers? They're usually pretty ex like hard and difficult to do and expensive. You can really only uh do I explained in my article how like the complexity of a logic analyzer it would normally require and I think I actually did do a previous uh design somewhere maybe I can find it like that had like it was all Ttl solution and it had like eight plugin boards like each like maybe eight bits. uh eight channels per plugin board or something.

They got a big control board. it requires hundreds of like chips to like do a 32-channel logic analyzer like this. so really difficult. uh you know a complex task to do it with discrete Ttl logic.

So really an excellent choice for a Cpld. and they've got like a little article thing here. it's got. It contains 96 registers, 32 universally applicable I O lines, four advanced inputs i can't remember what the advanced inputs did, three clock inputs, and a network that governs all internal links, global routing, pools, all inputs.

and outputs are Ttl compatible. Each input is capable of sourcing and syncing up to four milliamps. Uh, and it could go up to 90 megahertz. So yeah, I once again the maximum speed you could do with this thing depended upon the internal logic that you uh built into this thing.

And by the way, uh this chip came in two versions. Uh, it was. There was the Lsi 1016 and there was the Isp Lsi 1016 and the Isp one was hence like the acronym in system programmable. So as reprogrammable was the Lsi one.

It was cheaper, but it was mask programmable so you can only program it once and that was it. Um and the starter kit came with this little um, I think it might have been parallel port based or was it serial port based Up programmer that you could just program these chips so I made up a little like P or C C uh Zif a socket so I could program all these chips because I actually sold the chips for the Uh kit for this thing and so yeah, I made that all up and hooked it into the programmer and I could. You could reprogram these chips and you could do it for 150 bucks. Yeah, I remember the generic array blocks.

Uh, they had, uh each block has 28 inputs programmable x and or Xor arrays. Uh, four outputs which may be set up. Generic logic rocks. Yeah, that's why I said we had to use the external 574.

Yeah, it just didn't have the uh flip flop capability. It just had the generic logic blocks and stuff like that, the output, routing, pools, and things like that. So yeah, I can't remember like how many flip flops I had in this thing, but certainly you couldn't like use it to latch all the inputs. So that's why we both have to use the external 574 latch.

So why Laurent used this Sram: I I don't remember the Sram at the time, but I used mine because it was cheap, readily, relatively cheap readily available used in Uh pcs. As I said, it was standard 62256 case ram. It was 32k. Unfortunately, they only used up 4k on this.

So so mine was more powerful in terms of, uh, sample memory there now. uh, the Pc parallel port interface. Here's where it differs a bit. Um, Laurent.

obviously. uh, decided to, uh, latch in like data and have internal registers and latch those into the control chip. Whereas I didn't do that, we'll take a look at mine and he doesn't need much external circuitry here. There's a few gates around here, but yeah, basically an Lsr 245 latch and the oscillator down in here which goes straight in.

and bob's your uncle. That's all it is. Whereas my one I actually used two 8-bit serial expanders the 74-hct-259 and you should know that I'm a two Five Nine fan boy and I've used it in previous uh, Pc based uh designs as well. So I you know, like I just use that to latch all of my con.

These are all the control signals, so the software just basically just you know can change these Uh signals in real time, Which actually made the logic inside the programmable logic device uh, simpler. I used a 40 megahertz crystal oscillator. As I said, I don't remember why I use 40. instead of 50, I used some Three 90s to do the divider.

I didn't do that internally, whereas Laurent decided to do that. So I had a few extra Uh chips here. So we did implement the parallel port in a different way. But why did we both use the parallel port? Well, that was the obvious choice back in the day.

Okay, we could have uh, used the Rs232 serial port and we could have used a uh, like a Rs232 chip and then a micro controller to read in the serial data. but then you would have had another programmable logic device that would have been slow interface. Uh, because what? you know, 96 or 115 k board maximum right? and like and you had to send serial commands to the thing. No, it just wasn't a thing.

And remember, Usb didn't come out until probably like five years later I think 2001 and that was Usb 1.0 right? So Usb wasn't even imagined then. So it's like Pc parallel port based in the mid 90s was still the interface of choice if you want to interface to a Pc unless you designed like a plug-in Isa card or something like that. Um, yeah. so it's no surprise we both use that, but we did have, but we didn't implement it sort of in different ways.

and at the time, I don't actually recall if I actually considered putting this inside the programmable logic device. Whether or not I I don't know. I don't think I did. I think I just decided that no, I like having the two five nines.

I, you know. As I said, I was a bit of a fanboy of them. And yeah, and then it just made sense that we could just have the control signals like this. The controls had plenty of pins on the Uh 1016 Pld and you know that's it.

Simple, You know, I didn't want to have to like latch in like internal registers and stuff like that. So yeah, I just used them external. And here's my uh, internal logic inside my control chip and I like I always use like it's nice to use like dashed lines to like separate sections like this is the control logic section. This is uh, the post trigger counter.

This is the clock polarity selection. This is trigger selection. You know, trigger delay and things like that. So we both had a programmable uh, trigger delay.

Why? Because well that was like an advanced feature on logic analyzers and we've got our programmable logic device if we can fit it. Hey, why not? But here's a potential reason why that I maybe didn't include a lot of stuff internally that uh, Laurent did in his design. is that as I said, I got 32k ram. I had a bigger ram address counter.

I had like just more stuff to do inside the chip and as I said, I was already pushing like 95 to near 100 utilization of this device. In fact I had to mod. I can recall modifying the design and making it fit and go. Whoa.

Yes, I made the Bastard fit. You know it was. It was quite an effort to get it into that chip because uh, you know it was. These were limited resources chips you couldn't Just like.

You know, all this stuff here just barely fitted. So as you can see there were like flip-flops inside the device. but they were like limited in terms of uh, functionality. But you know there's like plenty of muxes and gates and things like that which you can wire in.

But that's my once again I won't go through the whole operation of it. but yep, that was tight as a nun's nasty that design. Let me tell you. all right let's have a look at the trigger unit here, shall we? Here's my design.

Here's Laurence Design over here and this is what's inside the 1016 trigger chip. Now I've used two 16-bit shift registers over here. data and clock input. They are cascaded like that so only require one data input and this is how I was able to uh, set the uh, the inverse polarity for each channel.

You know, select the polarity, trigger polarity for each channel and what I call a mask a channel. That means enable or disable a particular channel that you want to trigger from. So you obviously had to get all this data inside the C, P, or D. Like, you couldn't do it.

There just wasn't enough pins on the chip. you couldn't do it parallel so you had to do it serial. So just simple serial data clock coming from the in this particular case came directly from the Pc. Uh, control.

Those 74 Hc Hc259s I believe that directly came from didn't go through the control chip. It was completely under software control. So the software talked directly to the trigger chip itself to actually set it up. and you'll notice that I like, once again, use the dash separators to separate this into you know, a really easy to understand group.

So, the mask and invert shift registers, the inverse, the invert comparator array, the mask array as I called it, the grouping array. It was just one big and gate basically. um, why I showed them separate. It just looks nicer I guess and data output marks I can't actually remember why I needed a data output marks.

but anyway, here's the data input. Okay, coming from those latch chips and that you know that goes to your data input like this so that you can trigger from it. But why I had to latch them. Oh, that was to read out.

I think that was to read out the data because they were all on a common bus. That's right, they were all on combobus so you had to read the data back out of memory and you couldn't do it in parallel. So I read the data out in series like that. So I included that in the trigger chip, not in the control chip, the trigger chip because I already had the data lines there and the data lines were.

Or if you look at the system block diagram, won't go back. But if you look at the system block diagram, you'll notice that the data line is. It's basically one big data bus which connects the trigger chips, the memory and doesn't go into the control chip because we don't. Basically it's the trigger chip and the memory, so it bypasses the control completely.

So that's why I put the data output marks, the read, the readout mux inside the Uh trigger chip. It might seem odd, but that means you didn't have to wire yet another bus on the Pcb over to the Uh control chip. So yeah, it was just easier and hence why I could get like a single-sided layout because I didn't have buses running everywhere anyway. And if we have a look at Lauren's design here, it does exactly the same thing.

The shift register. Like this: 32-bit shift register 16 of them are for what he calls enable, which is probably a better name I I just called a Masqueray and the other one is a level array. You know, it's sort of like polarity. It's the same as my, um, inverse comparator array because you want to know whether or not you want to trigger off a positive off a one, or a zero for each of the in this case, 16 channels.

We both fitted 16 channels inside one of these logic chips. Why? Because that was basically based on the pin count pretty much and you probably couldn't have fitted any more circuitry inside anyway, even if you did have the bigger pin count. But yeah. Anyway, yeah, we both implemented that.

Absolutely identical because we had to get the seri. You just did not have enough data lines coming into this chip. didn't have enough pins to get from the control logic chip over to the trigger chip. You couldn't just have like 16 parallel lines.

In fact, 32 parallel lines just didn't have the number of chips. so you had to do it serially. Um, he's done the serial load a bit differently to how I've done it over here. I've done it simply just use one data and one clock line.

He's used four lines for some reason. Not sure why Anyway, and he's got like system clock going in there. I didn't care about the system clock. Um, I just yeah, I really didn't care at all because the trigger was independent of any of the system clocking stuff.

And over here, he's implemented his uh, logic his trigger logic differently using different gates. But this is whole. This is the whole like De Morgan's theorem thing. If I, yeah, I've done a video on De Morgan's theorem.

you can implement exactly the same logic using different configurations of gates ands ors, nands, you know, nuts, exclusive. All that, you know, you can implement it different ways. I just happen, uh to implement it with the grouping array as one big and gate. He did, but one big or gate here.

And yes, this in greater than or equal to one is the Iec standard symbol for an or gate and the equals to one. Here is the exclusive or gate and Anderson. And and um, yeah, it was. Just maybe leave in the comments down below.

Was that a publishing standard in Europe at the time to use Iec symbols? I know here in Australia we use the your uh traditional symbols over here and it would have been interesting to know whether or not I if I submitted my design using the Ise standard symbols, would Electronics Australia have redrawn it as this? Maybe just to keep like the style standard um kind of thing for the magazine and I can remember at Uh university at time in digital logic. uh of course, can't remember what one It actually both myself and David Bulfoni. We both failed. Um, both failed and uh like it was a like assignment thing.

Uh, we submitted our assignment and we used Iec symbols and they and they failed us because they had no idea what the their faculty, their lecturer, whoever was had no idea what Iec symbols were. They went, what's this rubbish? This is not. Even though we got it actually correct. Um, we we.

we were just like fanboys of of the Ic symbols at the time because it was being pushed heavily and I you know. anyway. so yeah, fail, That's that's interesting. Failed the class anyway.

I decided. you know the publishing standard in Australia at the time was to use your traditional logic symbols, not the new Iec standard stuff. But anyway, leave it in the comments down below. what did you use in the mid 90s Anyways, yes so lament.

Did it using one big or gate. I did it using one big and gate and then of course you have to use the exclusive or for the level control and of course used in the exclusive or gate here for uh, once again, he's only showing one. but this is actually done like you know, 16 times for the entire thing. Uh, whereas I actually displayed them all down here so you know the exclusive orga.

You pretty much have to use an exclusive or gate because that's a controlled inverter. Basically is what an exclusive or gate does. You can make it up with lots of other gates, but why bother? Um, Anyway, exclusive or gate? So uh yeah, so that's equivalent to my invert comparator array here and you can see they're exclusive. Um, well, exclusive.

Nor he's got uh, exclusive or but once again, like whether you use a an X nor or an X or doesn't really matter, it all comes out in the wash. It's all De Morgan's theorem and simpler for simplification and all sorts of stuff. And uh, then the enable array over here was an and whereas I used an or so it's it does exactly the same logic we both implemented. We both we're in the same mindset of thinking exactly how to do this, that we need a a controlled, you know, inverse array.

We we need a masking or enable array and then we need an A grouping thing which groups them all together. and um, and then we need to control it all with shift registers. So these are practically identical designs. They just the the logic just slightly differs, but it's absolutely equivalent.

So we both did exactly the same thing and has Laurent done the mux in? Yes, he has, He's done the multiplexing down here. I've done exactly the same thing. So once again, we're in exactly the same mindset. because you had to have the all of your 16 or 32 channels coming into the trigger chip because you need all the channels so that you can trigger it from them.

You've already routed those on the Pcb, they're already inside the chip. It makes sense to put your readout multiplexer there. Um, so yeah, he's got a lot of extra stuff in here. Not sure.

You know all sorts of uh, control stuff, chip select stuff, and things like that. so I'm not sure. Maybe that's to do with like, the, uh, multi-channel expansion and stuff. yeah, something like that.

whereas mine was all like integrated into one design, whereas he had to account for. you know, having multiple boards are cascaded together multiple 16 channel boards. But yeah, we're both doing exactly the same thing. and I guarantee you that would have been the reasoning.

Is that like it's a Pcb layout thing and just just general engineering optimization? We both would have thought, yep, we've got the signals inside the trigger chip. Why not read the data out from the trigger chip Because it's on the same database? We've already used our Pcb lines coming in there. So yeah, we were absolutely in the same mindset. These are practically identical.

Uh. designs. Absolutely, Absolutely. Well, you could say it's remarkable, but it's not really.

I mean, this was like logical conclusions of any design engineer doing this sort of thing once we came up with the same design. okay, we want to use. We've got this great new Lsi starter kit. Really cheap.

What can we do? Let's do a logic analyzer. It's going to be Pc based. It's going to have you know, 16 channels per logic. Uh, control Lsi chip because that's limited by the pin out and the internal uh functionality.

We've decided we've got the 16 channels, so then we're both going to go. well. We've already routed the pins to that trigger chip, so we might as well read our data out. From there, it's already connected through to the memory bus and like it.

It's not surprising at all that we came up with practically the exact same design, except that we had different logic. I, you know, it's just it's funny. but it's not surprising. And here's the second part of my article here and it just like has internal photos of the construction and the Pcb overlay as you can see.

Uh, single-sided Joby which is a totally different uh to Lorenz design which he just went like from the get-go just went. Oh, double-sided um for both boards, multiple boards. Whereas I wanted to get everything all on one board and as you can see like there's you know quite a few links in there. Of course I couldn't.

You can't do a design like this with absolutely no links. There's just too many pain-in-the-ass data buses running everywhere and it's just too difficult. And that's why. Uh, it was really nice to be able to get or pull all the data from the trigger chips here because the trigger chips were already wired into the ram chips here.

So rather than you know, imagine having to get these this data bus here. Imagine having to try and get that like here. Here it is comes in here like this: routes around like that, into the Sram and then into the trigger chip like that. So imagine then having to try and, uh, run this from the chip to you know, some other readout circuitry or something like that.

There's no way you could have done this design on a single sided, uh, layout in that particular case. So um, yeah, I can kind of sort of now vaguely remember being very excited, like oh, how am I going to get this data out and then, yeah, read it out from the trigger chip because it's already in there anyway and you know it had a few gates left over inside and Bob's your uncle. So anyway, it's about taking measurements and stuff like that. There's a front panel you can do that yourself and the overlay.

As I said, uh, that wasn't a one-to-one is that? No, you had to scale that yourself, parts list, and all that, and of course, uh, well, that's it. Oh, that's all she wrote. Um, I know, I think there's another page somewhere else. But anyway, there you go.

So there you go. That's how well back in the day, you thought, hey, you know somebody's copied somebody's project here Which, but as I said, like, that wouldn't have been a problem. it's just a curiosity, uh thing. And because essentially, when you publish your design, it was open source.

So you know we were doing open source between before, like open source hardware, before the open term open source hardware was ever invented. Um, so like we've been doing published magazine projects ever since back in Wireless Weekly back in, like the 1920s 1930s. Things like that. So that's how far back.

like open source hardware? Open source hardware, Um, essentially goes. And you know it wouldn't be a problem if I copied his design. or he copied my design. They are like, uh, fundamentally different miners, more focused.

Uh, the hobbyist can build it themselves because it's a single-sided layout. This one's more professional. You had to order the double-sided solder mask plated through Pcbs and everything. This one was a bit more expandable.

Mine actually, um, used graphical software whereas this one actually used a text text-based software because you could, actually, um, the Ascii extended Ascii set Actually had You could draw waveforms using the extended Ascii character set. So done it all using that whereas mine was done. Uh, I used a graphical, uh, you know, graphical user interface. I could just fit all 32 channels on the uh screen.

which is why I probably didn't bother with any uh, expansion things. So that's interesting how you can have two different designers essentially publish, or you know, sort of identical projects in terms of uh, functionality and especially in terms of like how they implemented in all the uh, trigger and control logic and stuff like that and both use the same interfaces because they were the logical uh conclusion at the time. And yes, I know this is uh, transparent because the front cover is green. so it that's pretty funky isn't it? I like that.

Wow, yeah, look at that. that is that is spooky because there's the cover and there's the front cover. Must have some green on the back there too. Green swirl and yeah, no, it's yellow.

That's that's yellow. Um, but it treats that as see-through So there you go transparent cover that is fantastic. I like that I'm going to screenshot that so if you watched all the way through to the end. Thank you for indulging me on this.

I just wanted to like show the differences between uh, two different designs and it just so happens to be my one and we basically did it at exactly the same time and we publish without each other. You know, knowledge of the other design because well, we just didn't know about it back then unless you bought the magazine because there were no web pages. You know, the web was really in its infancy. But yeah, we just came up with essentially the identical design and published it because.

well, that seemed like the thing to do at the time. And the let us know in the comments down below if you would have done it a different way. remember 1995 no Usb? How would you have done this? What parts would you have used and why would you have used an Fpga Would you have used uh, discrete Ttl logic for everything? And as I said, just done on the multiple card plug-in cards and things like that, let us know down below or where there's some other method to doing it. Because my recollection back then as the mid 90s 95 like to do Fpga uh, stuff.

There was actually i, um, there was, um, another. there was an Fpga based logic analyzer project published like like six months or 12 months after my one. And that was done by uh. Peter Baxter who, uh, at the time I'd met him like um, six seven years ago or something.

Uh, in the end and he was like an Fpga like field. Uh, like he was like a Xylinks that proved uh, don't know if his Xilinx are out here, but he was one of the approved Fpga uh, developers back then. So you got all the tools and and things like that, But you know for your average, you know, a backyard hobbyist or a midnight engineer. To develop the Fpgas wasn't that cheap back then, especially and to actually use them.

I believe these are lattice chips. They they weren't that expensive, but as I said they weren't didn't have much functionality. Yes, you could have done all this in one Fpga at the time. certainly.

um, but it would have cost a lot more. I can't remember Peter's uh design actually. Aha, I found Peter's design. It was actually March 1999.

It was a lot later uh than I actually. uh thought. So yeah, it wasn't until like almost year 2000 before like an Fpga logic analyzer project came out. So let's have a quick quiz.

Here is the first of two articles presenting what is almost certainly the most complex project design we've ever published: A high performance logic analyzer which provides 32 input channels, sampling rate up to 100 meg samples per second. It's free standing using a low cost compute to monitor display and also drive a printer or download captured or Pc. I can remember being impressed with this. I didn't know Peter at the time, I only met him like, you know, decades later.

Um, and yeah, I was impressed that it actually connected up to a Vga monitor at the time. Like that was just like, absolutely stunning. So oh geez that. that's really.

geez. We're really going to town now. Look, you know, gotta have the fans on there. So yeah, really, really serious business.

What does it use? Sorry, I don't think I can rotate this once again. Use the same 6256sram that I did and uh, binary to grade code converters, address bus time stamping. You could have rising edge, falling edge trigger. uh chain.

There's the Xor chains trigger, so you know. Yeah, I don't think there was any uh, external pattern triggering. But anyway, yeah, there it is. Altera.

Um, Efp 81 500 Programmable logic device, hands up if you remember that there. Yeah, Uh, sorry. 81 Yeah, 81 500 Both the uh control Fpga and the data capture Fpga as he calls it uses a Z80 Cpu down in there. so you know I really went to town.

it was and I remember he sold a kit for this thing but it was yeah. I think yeah that was one of the most. as they said like the most complex project ever published in Electronics Australia magazine. I think.

wow oh look at this. he still uses seven, four, five, seven, four, winner winner chicken dinner. but now like he had like external uh, probe interface uh type things. but yeah, it's still there.

see even back then probably why wouldn't you put the 574 latches inside the Altera Fpga Oh sorry, it's not an Fpga it's programmable logic. It's a Pld. Sorry. So yes, um, probably no wonder it couldn't Why beca, were they still that expensive? A solution in 1999 that you could? you know, I'd probably develop this in like 90, start this in 98 or something.

Perhaps that. were they still so expensive that you, you know, had to use the lower cost pro and less flexible uh pld the programmable logic device. And once again, because of the lack of the Fpga. uh, you know, fabric.

uh, inside, not as flexible. hence why the use of external Uh. 74hc 574s. they still could not get that you just didn't have.

He had flip-flops internally, but not the in the numbers required to do all of the latching. So anyway, I hope you found that as interesting as I did. and leave your thoughts and comments down below. And as always, uh, you can catch me on the alternative platforms.

You can catch me on the libraries and the bit shoots and the vimeos and the daily motions and the uh, whatever, there's another one a d live or something? I don't know, I'm on everything. Catch you next time you.