Hi welcome to the Eev blog! an Electronics Engineering Video Blog of interest to anyone involved in electronics design. I'm your host Dave Jones hi I Was just working on a design that included a an Actel igloo Nano Fpga one of the smallest Fpga on the market and uh, it also had a Xyl Linkx Spartan 3 Fpga in there as well and I haven't really done anything on Fpga before and everyone's been asking for something so I thought I'd just uh Cobble together some uh, basic notes, uh, really, just some comments on implementing uh Fpj. They're a little bit random. It's not exactly a step-by-step thing, but hopefully there's some good stuff in there.

How you can just uh B take a basic look at the data sheets uh, what you do at the schematic uh level to get the Fpga working and then some layout stuff as well. It's a bit random, but hopefully there's something good in there. It's about an hour long, so hang in there. Okay, we're going to start out here by assuming that we've already picked our device and it's going to be an Actel igloo Nano part Uh, it just so happens that for this design, we need uh, something that is, uh, very small, a small number of IO, a small number of logic, a real small amount, and uh, preferably very low power.

and the uh actel Igloo Nano pretty much, uh, ticks all the boxes there. So let's take a look at the actual data sheet itself now. Uh, it boasts uh, it's Nanop power consumption and it it's a 1.2v to 1.5 volt core logic uh power supply which is great. The lower the core voltage means, the lower power it's going to operate.

So um, so you can. If you can operate from 1.2 to 1.5 volt core voltage, then, uh, if you're really after ultra low power, you're going to want to use 1.2 But as you'll see later, there's a trap for young players there, so beware. We'll go into that later. But uh, it.

Also, it's a single Supply Uh system device as well. Which means that the whole chip itself can run off the one voltage. A lot of high-end Fpgas will actually require many, many different um, uh core voltages for various Uh aspects and functions, but this one can operate off a single voltage in this case, from 1.2 to 1.5 But we'll take a look at that. Um, and we will, uh, take a look at the various devices down here.

Now, what we need to look through here. This is a this is a parametric device table for all of the igloo Nano devices in this series from in this case uh system Gates Here is is your basic bench line of the part you're going to need. Now we know for this design that we it's a very small design. We don't need much logic at all I know it'll definitely fit in the 10,000 Uh system gate design so will be using today the AGL N10 device.

Now it's got uh, the equivalent of 260 what actel call Call versatiles um, but they're effectively uh, basically D flipflops or configurable logic which we'll look at uh later. equivalent macro cells 86 that tries to that tries to be a comparison with uh, the competitors like Xyl Linkx and Acro and um, Altia who talk in terms of macro cells in instead of Acels Versatile so it's very hard to actually translate logic density between the various devices and how many resources you'll need and things like that that can actually be quite complicated if you're uh, if you're design is a very tight fit inside your Fpga and uh, it's got a flash freeze mode. Excellent 2 microwatts consumption. Fantastic.

Doesn't have any internal uh RAM at all or any um, fan clock plls or anything like that, but we don't need anything like that. Uh, it's got four what they call verset globals but uh, globals in Fpga What they're talking about there is they're talking about global clocks and we'll talk about those later. and it's got two different IO Banks which uh for this design might be handy because we want we may want to operate um the different IO banks at different voltages and we'll take a look at that as well and look, it comes in a uh, it only has 34 Iio I do believe. Uh, don't quote me on this, but this could be the um the smallest Fpga in the industry in terms of Uh, size and pin count as well.

cuz Fpga are basically um, really high pin count and high uh logic density actual devices. but this is one of the smallest on the market. It's available in the UC 36 package which Uh has. its good and bad points as will see.

and if we go down to here the Ios's per package. here's our part again and it's uh available in the Uc36 or a Q48. It's the only part which is available in the Uc36 package there. the uh, larg logic uh density devices aren't available in that and that's a bit of a shame because if you only need a small number of IO um, it basically uh, forces you to choose the smallest logic density device.

Why can't you have a larger density device like the AGL N2o in that package? I don't know. Good question you have to ask Actel Micro semi um uh but you'll see that the other devices are basically scale up into larger uh pin count packages so you can't get these high density ones in these. Um, in smaller uh in smaller packages you you basically go up in size. Um, once you meet logic density and that's pretty standard in the industry really.

And if we take a look down here at the Uc36 package that we're going to use 3x3 millim it is Tiny 9 Square mm total and it's got a pin pitch of 0.4 mm. Absolutely tiny and can be a real pain in the ass when you're trying to solder this thing. And here is a good Uh representation telling you what, uh, versatile, what you can do with one of these uh, versatiles, each one of those building blocks inside the Fpga uh, they're also called macro cells in in other Uh products and they go under various other names, but you can do like in this case a three input lookup table uh, logic thing or you can do a D flipflop that has an an actual clocked individually clocked flipflop which has Um data and clear and once again, a more advanced Uh D flipflop with a separate enable pin And that allows you to do a whole bunch of stuff and you can build up your design based on these basic Uh flip-flops and uh, logic element lookup tables. They're very powerful and very versatile.

As the name goes, versatile, go figure. Just a quick note with ordering parts here, it actually can be quite complex. This one's relatively easy, but some of the more advanced Fpgas can be a real pain in the ass. and you've got to make sure you order exactly the right part number with the right Uh letters over here like this: if you don't do it, then you'll end up ordering the wrong part from Digi key or mouse or someone and you'll end up with the wrong package or something like that In in this case, the first part here is the model number of course, how many system Gates you got, Then you've got this digit here which it says V2 is 1.2 to 1.5 Vol Supply So if you wanted to operate at 1.2 volts and you accidentally ordered the V5 part, oops, it may not work, you might be in big trouble there.

Um, and the uh, you've got to order the Zed if you want the Nano uh, the the low power Nano device and V this uh one up here tells you what package type Um, in this case we're using the uh UC um microchip scale package, the UC 36 um, but you've got to choose the correct one for your you know for your particular build. otherwise you don't want to order the wrong uh chip and then you can't solder it on your board because you've got the wrong foot print. Oops, Um, and then of course you've got lead free as well. and the lead count as well.

But really, if you order um, that one, you know you. You pretty much know you're going to get the right uh, pin counts pretty obviously. And the temperature range as well. Do you want the industrial or the commercial temperature range? Um, most of the time you're just going to want the commercial uh temperature range.

but if you can't actually get that in stock, you can actually order the industrial temperature range and it just works over a wider temper. AG It's even better. Generally, they cost more, but if that's the only one you've got in stock, well, you order that. So just be wary that you order the exact part number you need.

And here's the basic internal Uh diagram of what uh, these Actel igloo Fpga look like. Now on the on the left and right side here, um, we've got the Bank IO they're actually the Io pins each one of those little pads. There is the Io Uh pin effectively and it's got two different banks Bank zero and bank one. Now don't worry about bank one at the top here and bank one down the bottom.

The smaller device we have only has the small number on the sides here, but uh, that allows having separate IO Banks Like this allows you to um, uh, operate those IO pins at different voltages. So if you're uh, trying to translate, say on the left side here, if you've got a 2.5 Vol uh IO bus coming in, you can translate that into say a 3.3 Vol on the uh, other on the right hand side here to bank zero and that can be very handy. Uh, and because all actel um, non actel Fpgas are all nonvolatile flash Fpgas which is different to the uh, volatile nature of the XY links and the alterior parts. Uh, you don't need an external configuration prom which will go into so that saves up board space, cost, and a whole bunch of other stuff.

Um, it's got the flash freeze technology built in, whatever that does Powers it down and it's got buil-in charge pumps to generate the high voltages required for The Flash and uh, any other functionality. and uh, these parts in the corner, these Ccls or Global clocks. Um, the Fpgas will have Global clock inputs and they're very. You must use those to Route efficiently route your clocks throughout the design.

I.E In the middle between all these little versatiles and we talked about the versatiles before. They're the little logic blocks which are used to build up your design inside this Fpga. But but Uh clocks are very important in any digital design and you have to feed those into the global clock pins. It's very important you can feed them into the Io, but then you get extra delays and it's got to go through the logic.

It uses up extra logic which could be used for your design and things like that. So trust me, you want to feed your Uh system clock or other clocks, whatever it is your working on uh into a global clock pin and then it goes between all of these uh elements and allows you to more effectively. and uh and Route your clocks throughout your design lower propagation delays faster, uh, faster speeds for your design and things like that. And if you're really curious to see what's inside one of these versatiles, the actual, uh, configurable switching elements in there that make up, uh, all that versatility.

Here it is. Um, this is not in the data sheet, it's in. As with all these Fpga it's everything's not in the one data sheet. They have application handbooks and in this case it's the Igloo Nano Fpga Fabric Users Guide and it tells you all about the Fpga what's called.

They call it the fabric of how the Fpga uh works and how it's made up. So there you go. Uh, follow that to your heart's content, knock yourself out. and if you're even Keener, you can get into the routing architecture of the Fpg and how you can route between various, uh, versatiles and run your clocks and things like that.

But uh, generally, unless you're trying to really optimize your design, uh, the Fpga tools will actually, uh, take care of this for you. But it's good to have knowledge of how these things optim uh, actually work and how you can optimize them. Uh, because it can be the difference between your your, uh, actual design in the Fpga operating at 10, MHz or 20 MHz For example, if you don't put the clocks near the Io or the banks that you want or things like that. so uh, just be aware that, uh, when you're designing with Fpgas you have to consider Often have to consider a lot of this stuff if you're trying to optimize your designs and you're wondering why you compile it and uh oh it, you know it's telling me it only works at 10 mega mehz and I wanted the thing to work at 20.

Oops. So there's lots of things to uh, consider. It can be a good read to actually. Uh, sit through and read these manuals.

Now here's a part of the data sheet. you really want to take notice of this: The basic recommended operating conditions for the various pins. So down in this, uh, left hand column down here we've got our pins VJ tag, V pump, and VCC pins and IO pins and all sorts of things and uh, what specs they operate at. Now let's take a look at our Um intended device.

Here is our 1.2 to 1.5 volt um power supply. Our VCC power supply core voltage can operate. sure enough, as it says, from 1. uh2 to uh basically 1.2 to 1.5 it's got a bit of margin uh there either side, but they're the basic operating things as you'd expect.

Now, the voltage for the JTAG pin, which we'll take a look at later. Uh, it can be in the range from 1.4 Vols to 3.6 Vols Fantastic. Okay, now our V pump uh, programming voltage. Okay, during operation can be anywhere from 3.0 to 3.6 volts cuz it doesn't care when the device is just operating, it's probably not.

Uh, it's not really used at all. But during programming mode, here's a bit of a trap. 3.15 to 3.45 or 3.3 volts. Uh, you standard 3.3 volts.

That's what it needs during programming mode. Now you remember back at the start we said this device was a single Supply voltage chip now. and in that in theory everything can run off the one Supply voltage or in this case say 1.5 volts. Well, that's true during operation, but during programming you can't operate this thing.

at 1.5 volts, you have to operate. You have that pin has to be 3.3 volts. so it's not really during programming mode. A true uh, single Supply device.

Because you can't operate the core voltage at 3.3 volts, you have to have a voltage regulator on there from 1.5 Well, what's what's the big deal I hear you ask? Well, that means that you've got to put extra uh DC to DC Converters on your board to cater for this stuff. and that adds to your bill of materials, Your cost, your board space, everything, so just be wary of that. It can be really annoying now. Uh VCC PLL Our chip does not have an internal phase lock loop, which is what a PLL is.

Uh, so we don't have to worry about that, but if we did, if we use one of the higher end uh Actel Igloo devices, we would care about that. And once again, it's from 1.2 to 1. Uh, Five, it must. The PLL must run at 1.5 1.2 to 1.5 volts.

It can't run off 3.3 or anything else. And our VCC IO pins. Uh, they can operate anywhere from 1.2 Vols to 3.3 volts. So that means that this device is not what's called a 5volt uh TTL capable um interface device.

So if you were looking at interfacing uh 5vt TTL signals to this this Fpga you can't do it. You would need a voltage level translator. so that's a bit of a trap. Don't assume that all Fpga are 5V capable because they aren't Now Something even more important than looking at your basic recommended operating conditions is looking at these little numbers here.

see these little uh asteres there look notes little note numbers. In this case, the VCC core note number four and five. Let's go down and take a look at what this has to say down in the fine print, shall we? It's printed under the table here, often in much finer print than what's here. So number four for Igloo V uh, 2 Nano device only operating.

Eh, We don't care too much about that. But look, look number five here. Real trap for young players. It says: the igloo Nano V5 devices can be programmed with the VCC core voltage at 1.5 volts only Igloo Nano V2 Devices can be programmed with the core voltage at 1.2 with the flash Pro 4 unit only or 1.5 volts if you're using the older flash Pro 3 unit and want to do in System Program using 1.2 volts, please contact the factory.

Now what this means is that you can be left um, up the creek without a paddle if you, uh, if you connected your call voltage your VCC core voltage to 1.2 volts as they claimed all the way back on the front page of the data sheet. They said it could operate at 1.2 volts and it can, but it cannot be programmed at 1.2 Vols You have to have the VCC core voltage at 1.5 volts during programming and it also tells you this. It highlights this in the flash Pro 4 which is the in circuit JTAG um, serial serial programmer for this uh for the Actel Igloo devices. It tells you that in the fine print in that user guide as well.

so just be careful. Don't believe everything you read on the front page specs of the data sheet and yet another thing to consider calculating power dissipation Beware of the figures that they use, that. 2 microwatt uh consumption figure for the flash freeze mode. that's assuming uh, these conditions and various other things Sleep.

Shut down, No flash freeze. Here's a table of the power supply configurations where the specs are valid and then it goes into quiescent uh currents during flash freeze mode and then you've got quiescent uh currents per IO Banks And things like this, It can get really complicated and this is a very, very simple Fpga. And here's an interesting figure: the dynamic uh power consumption in terms of microwatts per megahertz uh for for various um IO uh input, uh, buffer power and things like that it wow. You know it can get quite complicated and here's a more device specific Dynamic power consumption figures For the for various uh combinations of these, you'd have to go and check out the user guides to figure out what all these means.

The contribution to The Versatile used in a as a sequential module is going to have um, well, in this case for our design, 143 microwatts per megahertz? Oh, it can get bloody complicated. Good thing that they a lot of the manufacturers have um uh Power Dynamic uh power consumption? um estimate calculators to do a lot of this uh stuff for you, but often you'll have to go in here manually to do Bart calculations of um, uh, how much power your actual design your compiled design is going to take at a specific frequency and we haven't even scratch the surface. There can be very complicated stuff and this is not a complicated Fpga. but look at all this stuff you got to read.

oh my goodness. Well enough of that uh, data sheet business. Let's actually uh, do a schematic and see uh, the basic uh things we have to do to get a functional Fpga design up and running for something like this. Uh, very simple actel Igloo This is as simple as it gets.

So I Don't think other Fpga are this easy. Trust me, they're not okay as we might look at now. Uh, you'll see that I've placed the part here and before anyone asks what packageing I'm using, it's Altium designer. Okay, no more needs to be said now.

Uh, we have the two different banks now. It separates Uh Bank zero and Bank One into two specific uh Banks And the reason it does this is because down here in this one here, you'll notice that there's a separate VCC pin for VCC um input for Bank zero b0 there VCC in for input for uh bank one. So you have a different power supply voltage. So this B0o pin C5 there Powers the Io pins on this bank, the other pin D2 there Powers Io on bank number one.

So if you were doing a voltage translation design as we mentioned before and you say you want to had a bunch of IO and you wanted to bring them all into this um Bank zero and you wanted to operate that at say uh 1.8 volts or something like that, you would tie C5 to 1.8 volts and if you wanted 3.3 volts output, you would put all your our output pins or your other IO pins on to bank one here and then power bank one from Uh 3.3 Vol So you can. Uh, generally that's just very versatile, but in most designs you'll generally be operating from a single power supply voltage. So in that case, you might say put both of those pins to 3.3 volts now. Um, I'll copy this over into a working design and uh, see what we have now on these Banks Here these each IO pin is capable of not only IO, but lots of other stuff as well.

and they generally um, in the in the Uh pinouts for the device, they will tell you and some of these pins can have four, five, or six different functions on them. They can be incredible. Now in this case, because we got a very simple Fpga here. Um, only a couple of these pins have different purposes.

You'll see that Uh pin A4 right up the top here is Uh GDC 0 or uh, global Clock zero and once again, you can go in and figure out what these things mean. There's lots of lots of obscure names and they change from manufacturer to manufacturer, but generally if you see the Uh the term G there, you can, uh, generally sniff out that that is a global clock pin and that can be very, very important. Uh, as we'll talk about now down here, Um, well as you can see, there's other pins in bank one, another two Global clock pins down here, plus the FF pin if you go to the data sheet, that's the flash freeze pin. So uh, if you want to enable the flash freeze functionality, say you want to have a switch on your board or controlled from other circuitry, then you wouldn't be.

You may not be able to use that IO pin. You might lose that PIN for the flash freeze functionality and once again, for the global clocks, you can either use them as IO or clock input. In this case, you might want to use your main oscillator might be fed into Global clock zero here and in in that case, you would lose uh one of those IO pins for that functionality. Another major thing that you're going to have to deal with is the JTAG programming interface.

Now, because this is a flash-based device, uh, we don't have an external prom here, which I'll show you another um example of a zyink part that needs that external flash prom. but in this case, we can hook our JTAG program programming uh in circuit system header header connector here directly up to the JTAG pins on the Fpga and there's five pins here which you need to hook up. These are a JTAG Uh standard JTAG stands for uh joint, Test action group and JTAG was originally originally designed for uh in circuit um testing and Boundary testing of the Io pins of the device. So after you've assembled your board, you hook up JTAG and you can actually test that there's no shorts on the output or something like that.

Um, but but really, it's uh, morphed into like a generic programming interface for the device. So this is how you program uh, your, um, your design project into the flash into the acil device itself is via this JTAG interface. Now, Um, this it will. The header you use will totally depend on the JTAG programmer you're actually using.

Uh. In this case, we're using a flash Pro 4. That's what this pinouts for and that that's an Actel. That's and that's the genuine Actel flash programmer.

But you can use others on the market if you so desire. and they may have different pinouts, so make sure you get it right. And don't confuse TDI and Tdo uh, input and output and things like that. Now you can actually, uh, daisy chain devices together.

So if you've got more than one Fpga you can actually, um, daisy chain the input and output pins and you can have basically as many Fpga or other devices on that one JTAG uh, serial bus. And next, we've got the various size core and IO voltages and the JTAG and the voltage pump. Uh things. Now we've mentioned that the uh, different banks can have different Iio voltages.

In this case, I've got them both the same at 3.3 volts, but I could go in there and change that to say uh, 2.5 volts if you supply 2.5 Vols, or 1.8 or any other core voltage you want. And of course, you're going to want a bypass capacitor on each of those voltage pins. Now, Sometimes because this is a very tiny device, we've only got one pin, but sometimes you might get four, five, or or even more pins. Um, for that one, uh, voltage bank and they all have to be tied to the same voltage and, uh, preferably, um, maybe potentially even very high speed Divines designs.

Um, you may have to individually decouple those pins as well, and we'll go into that when we lay out the board. But uh, for most generic designs, especially on a small package like this, you you know you're going to get away with just well. you will. Um, cuz there's only one pin.

You just need the one bypass cap per pin. Or you could even tie them together and possibly get away with just one bypass cap for both pins. But it depends on the location of your bypass cap. If you're using ground planes, what speed is your design? Al all that signal Integrity stuff all that nasty stuff.

Um, that, uh, is. you know, really hard to know unless really hard to, uh, model even. Uh, you really have to know what you're doing. But don't let this scare you.

Okay, a by pass cap uh per pin like that is going to do the business no problem whatsoever. And over here we've got D3 and D4 they're two uh VCC pins. Once again, bigger Fpga You might have a dozen VCC pins You have to tie a dozen core voltage pins, but in this case, we're happy with just that one now. Um, because we got two pins.

I'll use two bypass caps on there I'll mix it up a bit I'll put 100 in and a 1 microfarad on there just for a bit of extra capacitance. Um, the main core? Uh, generally. Uh, you will want that. You've got to be careful.

Uh, especially on say, the Xylin devices and big, um, nonf flash-based devices. They can have very large uh, startup currents when you when they actually program the thing at startup and you need a lot of uh bypass capacitance, a lot of bulk capacitance there to actually handle the charge. But once again, don't let it scare you, don't get buried in the details there. and uh, we want to power this from 1.2 to 1.5 I've actually got because this is a prototype board.

I've actually got a COR a core voltage select header here so we can actually program the thing. You can move a jumper across, program it at 1.5 Vols and then put it down to 1.2 Vols But if you were designing this into a more intelligent um uh system, then uh, you would maybe have a fet in there or something to control your DC Todc converter which automatically selected the voltage during programming. and actually, that's what this uh pin this unused pin 4 up here up on the JTAG adapter is designed for exactly that purpose. It's designed for driving a mosfet which then can control the output voltage of your DC Todc converter during during the JTAG programming mode and then so it switches up to 1.5 during programming and then down to the minimum 1.2 during operation of your device so that you can draw the minimum amount of power consumption.

Or if you didn't want to worry about all that crap, you just tie the thing to 1.5 volts. No worries now. Uh, the JTAG pin here. This is the voltage that uh, you want for your JTAG interface.

So this E6 pin here actually controls the Io voltage on your JTAG interface here. Now generally most good Uh JTAG adapters can handle any voltage and that's why I fed back a sense line going all the way around here back to here. It'll have a voltage sense input so the in circuit programmer knows what voltage is being used. It can sense it and then handle the Io translation accordingly.

To drive the chip at the correct voltage, it's too hard and uh, in a specific case of the actel, it requires a V pump voltage down here on the E4 pin and that is supplied directly from the JTAG programming adapter and you can read all about this uh typical interface. It gives you example circuits in the Um in the data sheet for the JT programming adapter. in this case, the Uh the flash Pro four and down here we've got two extra pins which are the ground pins. Once again, just time to ground.

They must both be tie to ground. More advanced Fpg might have 20 or 100 ground pins I'm not kidding you and just on the power supply aspect. If you're powering Your Design from say a 5vt plug pack or any other voltage plug pack or some other Supply then uh, you're going to need a couple of voltage Regulators In this case, you're going to need a 3.3 volt voltage regulator for the Io if you're using it at that uh, generally you will be um, unless your entire system runs at 1.5 Vols then well, you can get away with just this. 1.5 Vol voltage regulator.

Now, as we talked about, this is where you may want to include that that fet in here to change the value of R28 here to change the output voltage between 1.5 Vols and 1.2 Vols if you wanted to get tricky and uh, just and and actually minimize your power consumption by operating your Fpga at 1.2 volt. so this is where you would, uh, do that in your DC Todc converter here. I've done it as a jumper because it's just a prototype Um board. But yeah, if you want to get fancy, some larger Fpgas can require three, four, or even half dozen different IO voltage for Io voltages.

For a typical design, it's crazy. You might have 5 volts. You might have some 5V logic stuff you might have 3.3 volts you might need. uh 2.

uh5 volts. Um, for some uh, phase lock loop stuff you might need 1.5 Vols you might need 1.2 volts. You might need 1.8 Volts for some other logic can get crazy. Get carried away.

even a basic design. A lot of chips. A lot of more advanced chips these days might only work at say 1.8 Well, in that case, you're screwed. You got to add another 1.8v voltage regulator to your design.

and that's something to think about up front when you're actually designing uh, your board. especially if you've got uh, uh, size constraints or budget constraints or something like that you don't want to be including half a dozen voltage regulators. And Fpga of course, aren't magic. They don't have any internal uh clocks that are of any use to your design.

uh, generally. So really, uh, your for your system to work, you're going to want to supply an external clock from either an oscillator like we are in this case. Here we go. We've got a 3.3 volt oscillator here, a standard packaged oscillator with its own uh bypass cap there, and uh, it might be say 20 MHz for a typical uh General Fpga uh, system.

something like this and you'll notice We've mentioned we're feeding it into a global clock pin. This is very important because um, if you feed it as we said, if you feed it into one of these IO pins up here which you can do cuz they are general purpose IO um and you can route those through to other parts of your design. but it's very inefficient in terms of Uh layout. It's very slow in terms of system speed and there's some uh.

In fact, there's some versatility which you can't get unless you feed the system clock into a global clock pin. very very important. Make sure you get it right. Otherwise you'll wonder why you hit the compile button on your uh on your Fpga design and it says sorry I can't do that or uh or your design only operates at 1 MHz Tough titties.

Now just as a bonus: I'm going to show you a different design here that uh doesn't use an ACO glue part. it uses a Zyink Spartan 3 part and it's the Um Spartan um X C3s 250e device Das 4vq 100c. So it's 100 uh pin quad flat pack package which is really quite usable. Really easy to uh, sold a package.

Now this is not a high-end Fpga at all. Um, in this case, it's only got four uh, Banks and um, you know it's it's a pretty, uh, not not super low-end like the igloo uh we were looking at before. But uh, it's certainly not a high-end Fpga device, that's for sure. It's quite, uh, cheap and simple.

But once again, look at these. We've got the same thing happening here. We've got the different thanks and you'll notice some of the things we saw before. We need a system clock like we just mentioned.

but it's got some weird stuff. What's this H swap thing? Well, you'll have to go to the data sheet to find out. Won't you look at this G- clock 11 there on Pin 91. All these all these Global clocks.

Ahuh, we've mentioned those before. Vref. What's that? You'll have to go to the data sheet to find out this lowly pin Pin 92 here. It doesn't do much else.

It's pretty boring. It's only got one generic IO And and uh, look at these other uh things here. Some of these pins are what's called Iio L5p and once again, same thing: IO L 5n Positive and negative. That indicates that this is a differential.

You can actually use these as differential. Um. IO not just standard single-ended Um, you know, 3.3 or 1.5 Vol IO They can be differential. You can configure them in lots of, uh, weird and unusual ways.

Poor old 92 there does nothing. They uh, they short chains that poor sucker and take a look on bank number one. here. we've got some other mysterious stuff.

What's this? RH clock? Well, that stands for rightand clock. And uh, that literally means the right hand part of the chip. uh of the physical die itself. And if you want to know what all that and what that actually means, you'll have to go read the Zyink data sheet for this device and the app Notes and the conf configuration.

what's his CSO look Pin 24 What's that do? Init B m Why have I got that Innit B pin tied High to 3.3 Well, there's a reason and it goes all the way down here. and it goes into the Uh the output enable and reset pin of a Zyink Fpga configuration device H time to look at the data sheet for that which we won't go into. we don't have time. but um, because this zyink uh, sparting three part is A is not a flash-based part like the igloo.

it is a ram based part. It needs a separate chip. This is actually a separate Uh configuration chip here. and in fact I think it's a 1 Point Uh, it's a 1 megabit um in circuit um, serial configuration flash prom.

So this external chip is what actually holds your program and when you power up your board, the Fpga is blank. It's dumb. It doesn't know what to do and it has to sit there and wait until some internal circuitry in the Fpga In this case, it does have its own clocks and things like that. for this specific purpose, it actually um, loads in uh, the configuration program which you've stored in your configuration prom here.

And once again, what's this little node I've got here? fpga configuration. It's in what's called Master mode serial and if you want to know what that is, you'll have to look at the xylin Fpga data sheet. But you got to know this stuff because if you don't get it right Um, then you then you'll build up your board and wonder why it just doesn't boot up. It doesn't load your program and things don't work.

and if you're a beginner can be a real pain in the ass. Um, but we're using Master serial mode. Which means you got to tie these pins M m0, M1 and M2 to low. And if you go up here and have a squeeze around here, look, there's the M1 pin combined with an IO pin.

So you lose an IO pin. Got to tie that to ground m0 there. Um, and M2 is uh down. I Don't know.

somewhere down here your guess is as good as mine. It's there somewhere there. it is M2 in that device there. pin 39.

You got to P tie those low to put it into a boot configuration mode that talks to this prom. It can get even more complicated than that if you want to program your device via an external micro or something like that. Crazy. What's all this? Uh, what's this IP stuff more VF Things read: WR Pins All sorts of stuff can get very complicated.

It's crazy and uh, once again, this will be fairly familiar to to you. It'll It's the JTAG pins the JTAG interface pins on the Fpga TDI Tdo. Now, in this case, it's actually it's hard to look at the configuration here, but this external prom is actually in series with the Uh TDI and TD lines um on the JTAG interface. In this case, we're using the Z Zy Linkx um 14 pin, uh JTAG interface and once again, they've got example app Notes of how to actually configure these devices and stuff like that.

But uh, just be aware that this is the complexity you got to go to just to start up just to boot this particular Zyink Spartan 3 Fpga. What a pain in the ass now. Um, as per the Actel igloo, we' fed our system clock here. our system clock.

You would feed into one of these Global clock. p Look at them, there's at least 11 of them. There's a lot, but in this case I fed it in all the way down here which is pin 40 which is the global clock too. Um, in this case, it really doesn't matter or it shouldn't matter which global clock I put that into.

Uh, but double check that in the data sheet Co because there might be a small trap there. Not all models of Fpga are the same, even if they're from the same manufacturer. Now here's an interesting one: I'm actually using the Um. This particular design design actually has the Altium JTAG interface as well and it's got what's called a soft JTAG interface.

Um, now you'll notice that the uh soft that the What's called the soft Tclock pin here. Don't worry about the details, but it's basically a clock pin. Now that I because it's a clock pin and I want it to operate, be fairly efficient and operate at fast speeds. I've ensured that the clock pin here actually goes into pin 32 a global clock pin.

So just be careful if you're um, same. if you've got say an SPI bus or something like that and you want it to operate really quickly. well, the clock pin, um, you might want. Well, you might want to hook up to a global clock pin.

Uh, just just be wary of that. or if you got some other uh clock based system. Very important. And that's why these Fpgas have so many Global clock pins.

It just allows you to um, uh, do really complex uh CL clocked really complex designs with multiple system clocks and things like that. And what sort of power supply voltages does this device need? Well, I'm glad you asked. In this case of the Zyink Spartan 3 I'm using um once again, different banks. Here we go: The Vcco Bank Zero Bank One Bank Two Bank three I've tied them all to 3.3 volts cuz it's not a multi voltage Um interface uh interface Design This one I've only used two bypass Uh caps because uh this is not a particularly high speed design.

But if it was, you might want to have um bypass pins on even every one of those pins if you really, uh, have to. So because these pins are spread out a lot, look and pin 82 is not next to pin 97 on the actual chip, right? It's not right next to it. If it was, then you can get away with the one bypass cap, but they've actually spread those pins um for for Speed reasons and all sorts of other really tricky stuff. They' actually spread those pins apart on the device and you'll notice none of them are next to each other.

So um, you know really highspeed designs. You might want to bypass cap for each one of those pins. It can get really annoying. Now we've got what's called VCC Ox over here.

Um, that's for auxiliary uh, stuff with inside the Fpga Read the data sheet if you want to know more, but it must be 2.5 volts. This is the only thing in my design that needs 2.5 volts. How annoying! I've Got to Now have a separate voltage regulator up here. This one has four 3.3 2.5 1.5 and 1.2 Vols.

Ah, how annoying because the not only do we need 2.5 Volts for the Um auxiliary up here, but we need 1.2 volts for the core. It doesn't operate at 3.3 or 2.5 So Bingo we've just increased our system cost and complexity Again by adding extra voltage Regulators there and once again, you might want to bypass each of those those Um pins I'm I'm going to get away with just two bypass Uh pins for each group of four power pins there. And once again, it has a whole bunch of uh, ground uh pins on the device, which you'll typically want to tie Uh directly down to your Uh down to some sort of ground plane on your bottom layer or an internal layer for a multi-layer design, especially if you got BGA devices. All right, let's take a look at the Actel igloo part here on a real Fpga This is a fairly small board.

It's only 50 mm x 33 mm. Couple of .1 in headers here. there's the Uh JTAG interface down here 0.1 in um, jeal row pin header down there. pretty standard, but look at the size of this chip here and a couple of 063 surface mount Uh bypass caps.

Let's take a look at the chip. It is absolutely tiny and uh, if we have a look at the Uh 3D view here, you can see that the Fpga itself is only 3 mm x 3 mm and it really is not much bigger than than the footprints of the two 0603 bypass capacitors here. Absolutely crazy. It's uh, that's how small this device, um, actually is.

It's one of the Uh I think it is the smallest Fpga on the market, but uh, I mean we can go for smaller uh, bypass? uh, caps there of course. But um, really, you know it depends on the design you want to do. This is a prototype, so I'm going to use 0603. Now the device, as we've mentioned, is a Uh 0.4 mm pin pitch.

So it's 0.4 mm between each one of those pins. Now this is a um, this is a standard Uh footprint for this. Uh, for this particular BGA device, it's 36 pins. You can see the tiny little pads in there now.

um, the first thing you're going to I want to do when you put this down is to figure out how you're actually going to, uh, route out or what's called. fan out the pins on this device and that is dependent upon whether you're using a double-sided board or you're using a multi-layer board. now. I'm going to put this on a double-sided board and I've decided to, actually, uh, completely fan out the device on the one layer and I can do this because it's only effectively uh, two layers deep on the outer Um pads to get down to the core down here.

Now, these are traces because, um, well. Fpga When you're Fanning out these sort of things, there's a whole tradeoff between how many layers PCB you're going to need when you're find out these BGA type devices as opposed to a quad flat pack or something like that which has all the pins around the outside and you can just, uh, route them out really easily. But because this is a BGA device, a bore grid array real pain in the ass and uh, this is why it's a massive tradeoff. um between your ability to Route out the traces and the minimum Trace width these tracers I've got here, they're only 0.1 mm or uh, just on 4 thou, uh, width and a lot of PC A lot of the cheap PCB manufacturers will not be able to do 4 traces if you want to go to um, you know, or or you'll have to pay more for that technology.

So even though we've instantly um, we we're using as basically as smaller um, we're using a fourth out track and space as it's called in between here. Then, uh, really, we have to, uh, pay a manufacturer who's capable of manufacturing a what's called a 44 um spec board fourth hour Trace fourth hour clearance and that doesn't include any visas at all on this design Now I've got some VES up here now. They might look, uh, like typical wires, but take into account that my grid space in here is .1 mm. Okay, each one of these grids and this VI here is a whole size, a drill hole size of 0.1 mm.

It's ridiculously small and it's got a pad diameter of 0.2 mm. This is really, um, you know that's quite Leading Edge stuff. Uh, you would be very hard pressed to get um anyone to do anything under this one here which which is a 0.3 mm uh, whole size or a and a 0.4 mm pad. Now generally you wouldn't do that because um, you would want to include a bigger ratio between the Via hole size and the pad size.

so you might want to increase that to say 0.5 mm like that. So you don't get what's called a via breakout. So the drill is not always lined perfectly and you don't want it to break out the pad so you've You' got to, um, take into account what your PCB manufacturer specifies in their uh tolerance there. but that's a 0.3 mm which for General boards you would not want to go below 0.3 mm drill size.

trust me. Uh, you get you're in for a lot of expense and um and special costing. Now this is a 0.4 mimer via size here, but um I would typically use on a dense surface mount board. I'll my standard VI will be 0.3 mm like this one.

Now if I try and drag that VI under this chip and you can see because it's only a 0.4 mm pin pitch I can't use a 0.3 mm VI under there. it's impossible I can't even use a 0.2 mm. or maybe I could get away with a 0.2 mm VI if I reduced the um solder Mast expansion which we've got here, but we'll talk about that in a second. if I want to uh, actually fan out this Fpga on different layers with VES I'm going to have to use a 0.1 mm drill size.

Maybe I can get away with 02, but it's just crazy now. Um. solder mask as I was showing in my solder in tutorials is very, very important here. Look, you can see that tiny sliver down there.

The manufacturer is not going to be able to manufacture that. Okay, there'll be no solder mask left. We've actually got a what's called a solder mask expansion here of uh, 0.05 mm or 2 mil or 2 thou. Okay, that is a very small uh solder mask expansion on a general board.

You might use say 4, but because this is a very dense uh chip. which by the way, this chip drives this entire design. Okay, you might have through hole Parts on the rest of your board. big through hole parts, massive uh pin pitches.

You can use 20 th tracks 20 th space. but because you've decided to use this little tiny piss, an Fpga and this pain in the ass uh, 0.4 mm pin pitch BGA package Bingo Instantly your uh to get your PCB manufactured manufactured you've got to go down to at least 4 4 th rules or if you wanted to Route out individual vies on different layers say this was a four layer board and you wanted to use the you know, drop through to the bottom layer to Route out some of those pins. Well you got to use a tiny little drill size like that now I could actually, um, change my solder mask expansion if the manufacturer uh actually could actually do this I could change it down to say one foul like that and you'll see it change. And in this case I might be able to get away with a 0.2 mm maybe.

but look at the solder. MK EXP expansion there. it's bugger all. so you don't want your paste.

uh when you sold of this in your solder paste to short out to your VI and you would want what you would want what is called a tented via so you'd want to go in there and you'd want to force tenting onto those VES like that so that uh uh, there is no solder mask expansion so when you uh, flip to the 3D view, you'll actually see the difference there. So if I drag, say two vies in here like this. Got my 0.1 mm one here, my 0.2 mm. this one has a T in on the top of the Vi top and the bottom.

So uh, if we go into 3D view here you'll see you'll notice that uh it's it. This is what uh one of the things 3D mode is really great for because it can actually show you the uh, the real solder mask expansion on the board and what it's actually going to look like. In this case, it's a blue solder mask and you can can see the individual pads there and the solder mask expansion. Once again, remember we've only got a very tiny, very tight tolerance 1 th sold to mask expansion on those pads.

The manufacturers going to choke when they hear that they're going to charge you a crap load of money if they're actually able to do that at all. But as you can see this one here, this uh, 0.2 mm hole here doesn't matter if it's 0.1 or2 mm what the size is, but because it's forced tenting on top of those, then um, there is no chance of uh paste. When you, uh, manufacture your board, you'll lay down some solder paste. no chance of it Short in to the Via next to it.

But look at this one here. It's tiny and that distance in there is only going to be less than 0.1 millimeters. It's tiny, so if you accidentally get some solder bridging across there, you're in deep trouble if you've applied too much solder pace. So really, when you're doing high density uh, BGA boards like this, make sure that you, uh, tent your Vs and you may actually have to plug them to.

You may have to get the manufacturer to what's called plug it and they actually put a little resin or something in inside to plug the hole first so that the solder M truly does, uh, cover it. But when you're talking about like a 0 point uh, 1 mm hole like this one which is insanely small, it's almost a micro uh via um, size really. So um, uh, generally if we go back in, I've just tented that one. There you go, it's uh, it's tented.

Just make sure you tent or plug them. otherwise you could end up with massive shorts under there and you won't be able to inspect it of course and you won't know till you to until you go. and actually, uh, power up your prototype and it could actually even go bang if you accidentally short out uh, ground and power poof release the Magic Smoke Oops Now I got a little bit, uh, sidetracked there talking about all that sort of stuff. but we're talking about Fanning out this Fpga either using Vys or uh, Trac say now because this is only two layers, two pin layers deep I'm actually able to get one Trace out there I can't get TR two really cuz we're already down to 4 TH or .1 mm track width.

but uh, sometimes on some Fpga especially on the larger uh pin pitch ones, you can actually get two tracks out between one individual uh pin. Now, if this Fpga was any bigger, we would not be able to Route out. Uh, the extra tracks here? we'd be forced to use some VES here to drop through to our other layers. Bingo We've instantly, uh, meant that we have to, um, get 0.1.2 mm drill hole boards.

Much more expensive, pain in the ass. But anyway. um, I figured out a way to uh, route or fan out this device. um, uh, based on and uh, just based on a single layer here.

So uh, if you'll notice each quadrant of the Fpga like this is basically a rotational mirror image of the one up here. Well, it's not quite, but it's close. sort of. This one matches that.

This quadrant matches the diagonal quadrant over there. and uh, so on. and uh, and really, it. it is quite a nice symmetrical rotational design.

I Like, it brings a bit of a tear to the eye. really. Um, so we've routed out, uh, these using four traces. Okay, let's switch to Imperial mode cuz I Like to use Imperial not metric mode for my uh tracer.

but for whole sizes and board sizes and things like that I use metric. go figure. Um, but yeah, that's just the way the a lot of the industry works. The PCB industry does mix up their uh, their millimeters and their THS quite a lot.

Um, but you have to generally juggle both when you're doing a PCB design like this. Anyway, Um, this means that we can, um, sort of start Fanning out. Um, these using larger traces, We might say go to a six th trace or something like that. that when we, um, take that because you don't want to use a four Trace all over your board so you might just fan it out with those small uh 4L traces or you could even, uh, say fan it out with say an Eow Trace Perhaps you might be able to get away with that, but just watch your clearances in there.

Um, if you don't have enough space there, we go. we might. Yeah, that's probably going to be enough space in there so we could fan this out with an 8 with 8 mm traces. No problems at all.

So there you go. that is. Um, basically, uh, laying out a or Fanning out a a Fpga A4 mm pitch BGA device. Really, if you can avoid it.

uh, using these type of packages and these devices do it because it can be really expensive and a real pain in the butt and uh, likewise. uh, we're trying to get our bypass caps here close to our uh, close to our power pins in here so you drag it all the way over here and then you might have say a uh a VI in here like this. Okay, dropping it down to a, um, dropping it down to, you know, a power tracer on on a different layer. but look, this is a 0.3 mm V which is the Um which is the minimum size I would be comfortable with on on a basic board like this without uh, paying a lot more.

Some people would even say4 mm is too small. Okay, but once I get in there you can see that routing out these becomes a bit of a pain. and then I've got to move my cap in here and uh, just it gets really quite ugly really quickly, especially if you got a lot of bypass caps on a design like this. Now a lot of Um Fpga design especially some more advanced ones will actually um, the bypass caps will be directly under the chip on the bottom layer.

uh, the bottom side of The Bard and what's called a um, what's called a two side Ed load uh components on both sides of the board so you can get a very low inductance path between your pad like if your visas here like this. Okay, I might swap my um I might swap my component down to the bottom layer down there. Okay, it's now flipped over to the bottom and I might sit that on the bottom like that. Okay, so I can actually get if this was a huge device like a massive big you know, four 500 or 1,000 pin BGA device I'd put that bypass cap on the bottom there and Bingo it's disappeared.

You'll find that it's actually vanished onto the bottom side of the board right next to the Vi. That uh allows me to get a low inductance path through to that bottom layer. but there you go. There's uh.

Fpga for you I hope you found that interesting. And really, this was a very basic implementation. a very L the lowest end Fpga you can get get and there's actually a lot of factors I didn't cover so please don't leave comments saying I left out this I left out that it's designed to be food for thought, thought and uh, hopefully you learn something. but go check the data sheets.

Don't be scared of these sorts of devices, just be aware that there's lots of traps for young players. A lot of things which: Drive Your Design decisions for Fpga not only on the schematic and the component level, but on the PCB level as well. Hope you liked it! I'll see you next time and don't forget to subscribe and uh, rate and uh, do all and comment and all that sort of stuff even if it's a flame comment I Don't mind, really see you.