I was going to use a PTC to limit the current to a motor driver, but when I started hearing about "latch up" I was worried that would happen if a control input was present while the voltage was being dropped (i.e. the PTC "tripped") but now I see it's as simple as adding a couple diodes.
Can you make a device that would give an electric shock, everytime it hears the word "Actually"? Then, redo this video, while wearing said device? I'd watch it….
Wow, Dave has been at it for a while, eh? I only encountered latch-up in my own project yesterday, while connecting a lead wire from the gate of a PNP Mosfet to an external frequency counting circuit. Sometimes the Mosfet would turn on permanently (when I moved the probe wire), despite the fact that the gate driver's collector was still oscillating … and despite the fact the gate was protected by a zener. Mysterious. Well, now I know … maybe all power MOS drivers need a clamp around the gates?
Thanks, you totally saved me, tomorrow I have an exam in VLSI and this subject always comes up in exams… Thanks a million man, you have put up there the most comprehensive explanation I have come across…
Would something like this cause an IC power rail to act like a resistor, I've had some cmos based chips that for some reason draw a lot of power but still somewhat function and a resistance is present on the power rails usually in the order of 40 odd ohms, my guess is the output mosfets latched up and "burned" in a resistance to the power rails
You did not mention one other common source for latchup problems, namely incorrect power sequencing for a board/chip (which led to my first excursion into latchup problems), I assume due to making the video shorter? Still important to know IMO
13 Years later. Thanks for the tip 😉
incomplete explanation. unprofessional . not recommended
12 years ago. Wow. Look hiw the channel has evolved over the years. Good job Dave !
This guy only got younger over the years lol
11 years later, still helping people out like me. Thank you for sharing 11 year younger Dave!
Great explanation!
I was going to use a PTC to limit the current to a motor driver, but when I started hearing about "latch up" I was worried that would happen if a control input was present while the voltage was being dropped (i.e. the PTC "tripped") but now I see it's as simple as adding a couple diodes.
Can you make a device that would give an electric shock, everytime it hears the word "Actually"?
Then, redo this video, while wearing said device?
I'd watch it….
Wow, Dave has been at it for a while, eh? I only encountered latch-up in my own project yesterday, while connecting a lead wire from the gate of a PNP Mosfet to an external frequency counting circuit. Sometimes the Mosfet would turn on permanently (when I moved the probe wire), despite the fact that the gate driver's collector was still oscillating … and despite the fact the gate was protected by a zener. Mysterious. Well, now I know … maybe all power MOS drivers need a clamp around the gates?
Still great video 10 years later
Great video. Simple easy to understand explanation of SCR latchup. Will help me overcome some troubles I caused myself with a recent project.
Thank you sir. You really explained very much. 🤘 😊
you didnt explain why they use scr latch up circuits i mean if its bad why use it in every circuit ????
Nice explanation. So that's why hotplug devices have longer power contacts…
ty
Thanks, you totally saved me, tomorrow I have an exam in VLSI and this subject always comes up in exams… Thanks a million man, you have put up there the most comprehensive explanation I have come across…
Would something like this cause an IC power rail to act like a resistor, I've had some cmos based chips that for some reason draw a lot of power but still somewhat function and a resistance is present on the power rails usually in the order of 40 odd ohms, my guess is the output mosfets latched up and "burned" in a resistance to the power rails
G'day, cobber!!!
thanks, loving this
Got it properly, well people told me this problem but no one answered an solution
the pmos region should housed in a n-well
Nice tutorial. Think you could do one on PLLs?
so a badly designed usb device/port controler could go BANG if you hotplug it?
You did not mention one other common source for latchup problems, namely incorrect power sequencing for a board/chip (which led to my first excursion into latchup problems), I assume due to making the video shorter? Still important to know IMO
Thanks, nice one – never knew that about CMOS before.
I love your videos and I've only seen two so far, you're brilliant
How do you know so much?
Thanks, I know you have over 200 videos now but I'm going through all of them from beginning to end. Very educational for a CpE student like me.
Thanks. I actually prefer these tutorials to product reviews, but that's just me. Thanks again.