Hi, it's Pcb layout review time again. I haven't done this in a while and this uh comes from the Ev blog forum from uh forum user so Fp G uh from Germany Hi to all my German viewers and has got this project and wants some opinions on a layout and I thought you know it's probably an interesting example so we might learn a thing or two here hopefully. So let's go through it now. Now what it is is basically an image sensor here.

We've got an Fpga here, which is a little uh, mark 32 Mark X02 in a 32 pin Qfn package here and then we've got a little microcontroller up there. don't know what that is? don't care, doesn't matter. Um, and we've got a Usb uart thing over here and a little buck converter over here. so this is not a finished layout.

this is just like an in progress uh thing that he did just a you know show like am I on the right track and he talked about stack ups and things like that. Now I don't know, uh the exact part uh, used in here for this image sensor, but look, it's a little 20 pin Bga in here by four pins. The only equivalent pin out I could find for this on Digikey, for example. looks like it's the right business.

I don't know, like I don't actually have the altium files to actually load in the proper thing. so we'll just go from the posted image. But you know this looks like uh, it's one of these image sensor things. He says it's uh, low or low resolution.

like it's you know, like a low end camera. So 640 by 480? you know it sounds pretty viable. So obviously, uh, doing some Fpga processing of the image, uh, taken from the sensor, probably in real time, doing some I don't know masking thing or running, you know, some sort of image detection algorithm or Opencv, or one of those uh, you know, image algorithm type processing things. And obviously the microcontroller here just drives that with an I squared C line.

But as I said, this layout is not finished. Um, so let's just talk about uh, several things of like stack up and other issues to do with routing and component placement and stuff like that. Because these discussions are always quite interesting. So let's go over and have a look at the board here.

All right, so let's have a look here. Now I'm not, uh, too concerned about the uh buck converter here. That's not really what I'm after. I'm more in terms of uh, like a compliant component placement for bypassing and layer stack up and just other uh, general things.

But actually, this layout for this butt converter looks really tight by the way. I'll just mention it for a second. It's about keeping your loop area as small as possible. Um, and here's the bypass cap.

and you know the traces are only small so I wouldn't have uh done that. and what's that? What's that down in there? Oh, you don't want like, yeah, put a right angle in there with a chamfer. You don't need the chamfer. It's okay.

Anyway, I'm not going to talk about the butt converter. obviously. We've got a Usb input over here and then an So package uart. Uh, you know, serial converter.

Looks like we have a trace length matched um, trace here for the uart input. You don't necessarily like. The distance here here is so small it's not going to really make a difference, but you know, if you want to do it. Decent practice.

I don't know why a everything else is surface mount on here. Um, except for the connectors and we've got a through-hole crystal. Why, um, I just would have used a surface mount crystal. Anyway, Okay, so let's start getting into the layout.

Let's assume that you know the uh, placement of the parts is exactly where they should be. Obviously, the image sensor goes in the middle and there's also this big and there's two big mounting holes and it's obviously more. you know, some bigger, uh, assembly that's actually, um, assembled on that. So we're assuming that that can go under that or is it yeah, because they're all on the top side.

so there has to be space under here because this shows this. Keep out for this module is like this. so I'm assuming that the components all fit under. So assuming that's all okay, let's just run with this.

so just start with the Usb uart chip here. You might think there's not much going on, but and this is a four layer board. He said he had to go to four layers because of the it couldn't really rout out the five, uh, mill, the five four traces in between these pads in here. I'm gonna assume he's got the pads fine.

He's done the clearance rules and all that sort of stuff. He said he couldn't route those out on a two layer board using the Jlc Pcb manufacturing process and that's uh, quite common if you have a manufacturer in mind. and there, the four layer process. tolerances might be different to the two layer process.

uh, tolerances. and that could be a thing. so you just don't get the you know you can't do five thou, five thou on a two layer. for example, I haven't checked.

That doesn't matter, let's just assume, uh, that's been checked and we've gone to a four layer now. Uh, ordinarily a four-layer board like this. Luxurious. It gives you plenty of options for like, controlled impedance traces if you need it, and you know good Emc and all sorts of uh stuff and routing, flexibility and everything.

Absolutely fantastic. So the first thing is the uh stack up, which is one of which is the first question he posted in the forum. Now for a layout like this, you might typically have power and you'd have power and ground in the middle. And if you're running, it looks like we've got some controlled impedance traces here.

We'll talk about this shortly. If you've got controlled impedance traces, the microstrip on the uh, top layer routing. this is inner layer. But anyway, we'll get to that.

Assuming it's on the top layer, then you would have then the next layer down. So the top layer would be signal layer. Your next layer down, the first inner layer would be your ground and then the layer below. That would be your power.

You typically wouldn't put signal power and then ground. It's still okay, but it's not quite as good as having the ground directly under it. Uh, because then it changes your loop area, bypassing, and all sorts of stuff we won't go into so top signal layer, ground plane, power plane, and then bottom signal layer. and that's uh, generally how you do it.

Now the first rule of this is and and I see it over here, which we'll talk about in a second and several other places is that you for a surface mount design like this. Ideally what you want to do is try and route as much as possible on the top layer. so you want to avoid any wires jumping down to the bottom layers and things like that. So do as much as you can choose your component placement, do as much as your routing as you can all on the top layer, only if you have to, then jump down to the bottom layer.

or you know, even one of the inner layers or something like that, then you would do that. So anyway, so that's the thinking you should be going into when you're laying out a board like this. and he's clearly done that up here. Look, he's laid out this entire block up here.

apart from this input trace going up here on the bottom layer, which is fine, even though that could have been done on the top layer, look that that could have been routed around there and across like that. and there's no reason for that tight tolerance against the edge of the board there. In fact, some of the component components are quite, uh, close to the edge of board and has got rounded. I'm just going to assume that he wants a fully routed round edge board.

there might be some you know fit to envelope reason for that, and that's fine, so we won't question that at all. But anyway, you can see that he's routed all of the signal, uh, traces all on the top without. so that's that's good. That's a reasonable buck converter layout.

We won't worry about thickness of traces and actual, you know, in like, real tightness of the loop area and things like that. so that's fine. So he's obviously had that thinking up there and that is good, but you can see that that sort of thinking has like gone out the window here. Um look these are like these are serial.

These are transmit and receive lines okay and it's immediately like jumped to the bottom layer here. like why why wouldn't you try and rout and why wouldn't you try and route your signal layers on the top like that So I would Typically you would reserve your top signal layer for your signal traces and then if you need you know okay this can't get through here because this power trace is going down here like this. But you then you could say that well all of your power traces like you know these ones and everything else. they should probably be on the bottom layer for example the bottom signal traces and then just pop up with a via there to you know to come up and then you've got all this routing room going through here like this to uh you know get your signals over.

So really there was no need to drop that down there and you know I I know this like the board's going to work. Either way it doesn't matter, this is not a complex route, it's more just getting in a good mindset of laying it out. So when you have to do a larger, a bigger more complicated board, you're not going to come a gutsy later by. you know, routing your power piles like this.

In fact, on a board like this, you'd be routing all your signal traces first and then doing power later. Except for the bypass in here and over here, which we'll talk about. I just moved my floating dave head here so it's like over that box. Anyway, all right, let's get back into it right? So let's assume that all the chips are placed like this.

I mean this one at a diagonal. This is a common technique. If you're to mount your chip at 45 degrees like that. Don't worry about doing that.

The pick and place machines can handle that just fine. There's no worries doing that. And for uh, square packages like you know, quad flat packs and uh, Qfps like this one, if your chip was down right against the board say you had like, you know as your chip down there like that, then you wouldn't be able to get all the pins out of the bottom in here, you'd run out of routing room. So it's common to turn them 45 degrees.

You'll see that on large Pcbs like graphics cards. and like, especially the older school graphics cards and things like that, you'll see like the main graphic uh, chip with, you know, a big old-school quad flat pack we've got hundreds of pins is just rotated 45 degrees. It just allows you to get your traces out at a, you know, a more reasonable angle. There's just more rounding rooms.

So anyway, after you've placed your chips like this, it's probably worthwhile placing your bypass capacitors because they're going to be important. and there's a bit of discussion about this on the forum and the criticality of bypass capacitors. and if we actually go into here for the Mark Xo Lattice Fpga let us have a specific power decoupling and bypass filtering for their programmable logic devices. And because this is a little kind of pissant Fpga it's not a little piss weak thing, it doesn't require you know, massive amounts of decoupling.

Uh, it's only got two Vcc pins plus a Vcc Ios. So you know, really Vcc you only need like this is not a big grunty Fpga It's not going to take huge gulps of current like when you power the thing up which some of your real big grunty Fpgas can and then you need massive amounts of bypassing and it's real critical and all sorts of stuff. Um, in in this particular case, like lettuce, you know they recommend very the use of 0.1 uh, you know, 100 n 10 n capsa per device power pin is a good rule of thumb, so it's it's not critical and of course I've talked about this as well. Beware of Esr and self-resonant frequencies, but you don't know that unless you have the specific simulation tools and we won't go into that for a little piece a week.

Fpga like this, you just like, you know, just I just whack like you know one or two, one microfarad capacitors wouldn't even bother with any point ones or anything like that or any 10 ends higher frequency ones. I just whack one large bulk decoupling cap through there. really. And it's You Know, they say it's going to eliminate the low frequency stuff.

It's going to do the high frequency stuff too. You know, generally maybe you might put a, you know, a 10 in on there if you you really want to. But anyway, this is not a critical design where, uh, bypassing is going to matter. We're talking about a tiny Fpga like this.

um, and the image sensor. I don't know, I haven't looked, I haven't don't have the full data sheet for that. We've only got like a little brochure, um kind of thing. and uh, these bypass caps are quite large, by the way.

What are they? Um, like they look like 0805 size with a large pad or something like that. Beauty? I don't hate those, you know, I like. oh, 402 rubbish or something like that. only if you have to.

Anyway, So this is one of the main things I wanted to talk about with this design is the layout of these bypass caps here and here. but in particular, the image sensor. This struck me. This is the first thing I noticed when I glanced at this image, I went, what? These are the bypass caps? He hasn't done any of the ground yet.

This is obviously the ground side. This is the ground side. This is the ground side. Haven't stitched those through yet, which you should, by the way.

Um, just as a tip, when you're placing bypass caps and you're routing them in there as a first step, put in the via or vias you need for the ground and the power and things like that, route those in because then you'll know exactly how much room you've got to route out. all of your signal traces out of here like this. Okay, so the first thing I notice is why on earth is this trace running around here like this: This is the bypass capacitor. This is the bypass capacitor for this pin here.

Wow. and this bypass cap is for this pin here. And this bypass cap is for this pin here and like. And this bypass cap is for this pin Here, it's all.

It's almost as if they've all been rotated like they should all be rotated like 90 degrees like this. And this is one of the issues that you have. Like you might, uh, your schematic. Of course when you uh, draw your schematic and you put a bypass capacitor per pin, it'll be C1, C2, C3, C4.

And then when you when it automatically imports those onto your Pcb, then you might go. Oh, I'll just place the caps anywhere and then the your net list will tell you. Okay, this connects through to here and you go. Oh, Okay, I've got to run a trace all the way.

No, this is where you have to think from the get go. that component placement is everything so especially in regards to bypass capacitors. Just like this buck converter up here, you have to get what's called a small loop area and that is the area from say this power pin here. Okay, this has to go through this trace here and that has to go through the capacitor through some vias here to the ground plane and then back to the ground pin on the chip.

I'm not sure which is the ground pin on the chip right, but it's got to go through and that is your total loop area. it's called okay and the larger you loop area. I've done videos on this the greater your Emc uh you know issues in terms of like uh, radiation and immunity as well. So the larger the loop area the more problems you're going to have So you want to minimize that.

So this capacitor. So this pin here. Let's say if we're bypassing this one, it should be this bypass capacitor here and if it doesn't match the schematic, well move it away and move this one here so that this this pad here is right next to here. Like this, this amount of distance is fine.

You know it's neither here nor there, so you simply route that directly through to there and then it goes through and it goes through to the power pin. You see how much smaller that loop area will be. And if you take this example up here, which is absolutely enormous, look at this. This loop area is massive and that goes through.

Uh, well. It goes through your ground pin and up to here like it's an absolutely enormous loop area. You may as well not even have the bypass capacitor in that case. Really, it could even do more harm than good.

So yeah, really. Um, yeah. I would you know. dedicate it if you want to have four bypass caps for this, uh, image sensor.

That's just fine. Just tie that one to there, tie this one to here, tie this one to. oh, there's nothing on that side is there? Then I would have put so I would have moved this one down to here, down under here. so I'd have one like that and another one like that and then run the trace directly down to the chips and then straight through.

Uh, Vias. I'd like a Vr in there, two if you want. You know, if you're really really fussy, but yeah, a Via there directly down to the ground plane, which is the layout just below it. and then you'll have the optimized small loop area for your bypassing.

and then you've got the same thing going on over here. This one's a bit. This one's a bit more awkward, but okay. Look, this is the bypass capacitor for this pin.

Okay, so that's exactly where I'd put it. I probably would have flipped it out that way just so that you could route those traces out. Because look right, you've already cornered yourself in here. right? With by putting this here, you've and putting all these power traces in here like this, you've instantly created a bottleneck where you have no choice but to route this out through this Via here and here and drop down to the bottom layer.

There's no need to contract and constrain yourself like that, so I would simply flip this capacitor and just move it in that direction there and have the ground pad over here, for example. And then you can get your traces out like that and then route your power traces on the bottom layer. Well, actually by bottom layer. Uh, because we've got a four layer board, we would have a power plane so you can use the internal power plane that can either be a split power plane.

I won't get into the intricacies of split power planes and split grounds and things like that. let's just you know, and power plane usually shouldn't be a problems When you start to split your grounds up and things like that that can be generally speaking be an issue. And once again, this power trace over here. it's instantly cut out all of these two two four six traces.

Like the seven traces. Okay, seven traces That had to be rounded out here. So you've prioritized one lousy power trace for against seven signal traces. and now you're forced.

because you put that power trace in there. you're forced to drop all seven like this down to the bottom layer. now. Uh, so you.

so you wouldn't make that sacrifice. And this is why I said route signal layers first and then worry about your power later. Especially when you've got the flexibility of a full layer board. But now I realize why he might have done this.

You see, we've got wiggle Wiggle Wiggle. Yeah, traces on here. These are to match the length. So this trace here matches the length of the one next to it.

Now, you can argue whether or not that is required. I don't think that's required in this case. It might be required if you've got a real high speed Mipi interface for example. but I don't think this is a mippy.

a high speed Mipi sensor. It's just a low end 640 by 480. It uses the uh, serial digital interface. Um, system.

Oh no. sorry. this is a parallel one. Sorry, no, it's looking.

Another one. This is like an 8-bit parallel output. You know, if you want to match the lengths and just because, that's that's fine. Um, and generally speaking, though, you don't want to waste time.

uh, like over engineering something if it doesn't matter if you want to, you know, muck around with your trace lengths and things like that. I know the tools can do them automatically and things like that and it's it. doesn't cost you a huge amount of time, but anyway. Um, let's not worry about why the traces are matched like this.

what? Uh, what you might be trying to do here. Let's assume that you do let match the trace lengths like this. you might want to match also. Uh, the impedance of things.

So you might be doing a controlled impedance, but these aren't controlled. impedance wouldn't be a thing for this particular design, but if it was, let's just assume if it was, here's a Satin Pcb calculator. This is a micro strip one where you've got the trace. oh sorry, I can't draw on that.

You've got the trace on the top layer and then the ground plane underneath and that's a controlled impedance trace. Now, the one in the middle where he's actually dropped through to one of the middle layers here because the bottom layer is blue and the mid layer is, uh, is the mid layer which should be a ground plane and or power plane. You could run these on the power plane. Uh, for example, like you you might want to run what's called a strip line like this, which has a ground plane up here, a ground plane up here, and your signal is sandwiched in the middle.

Now, I won't go into the pros and cons of stripline versus microstrip. It doesn't matter, but that might be one of the reasons that you do that. But in this case, there's absolutely no reason to be running to use one of your internal layers to do that. So yeah, I don't know what's going on there, right? I I would have Simply, I would have run all of these traces directly over there.

Trace length match them if you want. I wouldn't have added this much wiggling, but yeah, I would trace let match that. trace length match those. In fact.

actually the I was going to say I would have chosen the location and the layout, the rotation of the Fpga here to match the shortest possible paths over here. But anyway. Um, so yeah. it looks like we got these three pins here which have to go out.

That's just yeah. Another one over here. Is that another one? I don't know. So yeah.

like there's a combination. Look, wait, like this one here is going on. The blue that's going on the bottom layer. See that on the bottom layer, this on the inner layer.

No, you want to follow that, You know? Shoot for that Holy grail of Pcb layout goodness by having all your signal traces on the same layer. If you can, do it, avoid links. Holy grail of like single-sided Pcb layout for example, which Smd layout design essentially is, you're doing it like a single sided design and then filling in the rest. You know, As I said, like the power and other stuff, Uh, later with your other layers as required.

But you're essentially trying to shoot back to old-school single-sided Pcb design with Smd components. Because they're not through-hole components, they don't have the luxury of essentially a Via for every single pin. So really, so, that's a Holy Grail. So I would have simply routed all of these as much as I could as many as I could on the top layer.

That would have been my first priority for this layout once I've chosen the location of my chips and I've put some bypassing around here and I've dropped the bypassing down to the power and ground layers. Then we would have a whole bunch of empty space all in here and I would have routed out all of the critical data lines and the clock lines and and control lines and things like that. and you'll find that once you get rid of this power trace, get rid of this power trace here. You know, maybe you might want to instead of having the capacitor like that.

You might have it like that, for example. Or you know up here, for example, you'd have all this room in here completely free to route your traces across like that. And that's you. know you want to prioritize traces, especially if they're critical, like potentially they could be if you had like a real high-speed high-end image sensor with you know you might have might have to trace length and as I said, controlled impedance.

maybe you've got some other thing, you're running your Ddr memory or whatever you're doing and you know things can get a little bit critical. So yeah, um, rather than just like use virus just to drop everything down like I should, you should not be. Unless you're absolutely at wit's End and you run out of space, you shouldn't be running. So we've got yeah, one, two, three four five, six, seven, eight nine.

Yes, there's nine trace length matched. Uh, layers. So that's eight data lines, plus the clock or something like that. That's all good.

But look, I mean, you've got something like this, right? You've got this blue trace. Wiggle. wiggle wiggle. Yeah.

Over to here. jumping up through a Via, onto a middle layer, over to here, and back down to the bottom layer up here. And where does it go to? Does it go to there? No, Where is it is that? Oh, anyway, you know it goes up there. There's no reason to jump this through a signal layers through multiple layers like that.

Only a large design. you're getting right. At the end, you're at your wit's end. You can't possibly get.

You've been working a week on this layout. You can't possibly fit this last trace in. That's when you've got to go. You know, crazy buggers, Which by the end of the layout by the way, should only be left with non-critical traces.

You should be routing all of your critical traces first as a priority. So as I said, all the data lines, all the important data lines, all the important clock and control lines, and the rest which is miscellaneous stuff like this. For example, this microcontroller up here is obviously controlling this. the I Squared C on this chip.

It's got like an I Square C communication interface which is where you set up all the parameters and you know things like that and data rates. And you know whatever you set up in the sensor. So there's two two wires going over here. and look, look, look at how this is going right? This is.

Oh, look at, I hate these chips like that. That's a pad on the corner. Evil Evil. Anyway, Um, yeah.

Look, it's going over here and then it's jumping on the to the inner layer and then it's going over here. Let's jump into the bottom layer and then it's going back to the inner layer. over here, jet back to the bottom layer, back to the inner layer, and over to here. Wow.

Like, for starters, I could have continued to run that on the top, on the top, on the top, on the top, on the top on the top. And like, you know, So yeah, like jumping layers when there's no need to. Um, now of course, because you got a you Pro, you would have prioritized all of your data lines coming over like this on the top layer. You know you would run this around the backside because an I Squared C line be as long as you like doesn't matter.

It's not critical, and if the longer it gets, you just lower the pull down resistor. By the way, um, to uh, counteract the extra capacitance of the line. Especially so over a long trace over a ground plane or something like that. Anyway, so yeah, um, so I would have taken.

these are the two I Squared C lines. I would have taken just both of those. Where's going? Yeah, yeah, yeah. over to here.

Okay, so it's a little bit annoying. I think it's yep. Okay, so it's these two pins here. so that's annoying.

Um, but it's only two lines. So yeah, I would have like. maybe you could have said okay, oh no. see if you just dropped a Via from your uh, bypass cap down to your power layer, you would have room potentially.

but all your data layers are. So yeah, all your data pins would be routed out like that. so that's kind of annoying. and these two are just stuck in here.

These in this case, you would route this last. and because they're low priority lines, you would route them last. You know they're non-critical So yeah, you might drop those down to the bottom layer and then just have bottom layer going straight over there like that. But potentially you could have done it on the top.

but I doubt it. Um, because you've got to get some of these around here anyway. So off hand, we've got all these vias here. Like count how many vias we've got.

I reckon we could have got away with not not counting, um, the bypass caps. Um, we could have got away with a couple of buyers there, you know, three, four vias, something like that total as opposed to all these sort of stuff. And we would have lowered our loop area if we had our bypass cap going directly in here, and a via here going directly down to the ground plane below it. and Bob's your uncle.

So yeah, and you can just see all the all the messy business going on with all these power traces here. And then you know once again, the same thing. you've boxed yourself in here and you've got no option but to drop these four signal lines down to the bottom layer and then route them out like this. I I would have pulled these two lines early in the process.

even though they're non-critical early in the process. I would have gone. Oh okay. both of them say assume these are both lines.

Let's do a larger trace, right. Both lines like this, I just would have routed those around the bottom, there, and up to there. Is that where they're going Anyway, I would have like routed that first. Um, you know, Well, you know, fairly early on in the design.

uh, process. Just get those over and anything that needs power then I would have you know, well you would have had the bypass caps done already. But anyway, by the fact that you snaked all of these power traces around here, don't do that. The top layer should be for signal traces.

So this just looks like your Jtag interface here for your Fpga and like these traces here are going, you can see those they're going off to. Yeah, various ones. I mean, look, you've got this. this pin here.

dropping to the lower layer, going around like this. Oh no, it's not that one's that one. It's that one there dropping going around like that up here around here, around here like that. I mean, huh.

Why when you could have just as a priority routed that straight directly in like that? I mean, you know these bypass caps don't have to be here. I mean this. this Fpga you could have like yeah, once again, like I wouldn't have rotated that 45 degrees. Maybe I would have put it.

Maybe you know there something like that? Perhaps I don't know. Um, yeah, it's neither here nor there. Yeah. But the point is is that, uh yeah, all power traces on the top just don't do that.

It's just it kills all your routing room and leaves you zero flexibility and forces you to go on other internal layers and things like that. And unless you absolutely need to, you would not be running traces on the internal layers. Uh, why? Because you want to dedicate them to a solid power and ground plane if possible. from a signal integrity point of view.

uh, Emc and all that. it's better to have solid, uh, power and ground lanes and two you can't like. Check the traces. You can't uh, cut them, You can't mod them, You can't you know do anything like that if you're dropping them down to the middle uh layer.

So yeah, it's it's just much nicer and you can't follow them when you you know. If people have to like, you know, repair, debug the board like that. You can't follow internal traces and things like that. It's just unless you absolutely have to and you wouldn't have to on a four layer board like this with just like what you know, four chips on it.

Um, no, You'd be looking to get 90 percent of this layout on the top layer. all your signal traces on the top layer 5 or 10 percent tops might drop down to the bottom layer. You'd have no signal traces on the inner layer and there'd be no, even if you were needed high speed signal integrity. As I said, you would go for uh, your micro strip, which is, uh, the controlled impedance of the top trace and the ground plane underneath.

Or you could do it on the bottom layer for example. but then you'd have to swap your. you'd have to trade off the ground plane on a lower layer or you could, uh, you might might have two. You know.

and like I've like the odd design, you might go with two grounds in the middle and then run you. If your power requirements are simplistic, which they are. For this design, you might run your power on your top and bottom. Uh, for example, you might have like some flood fill power top and bottom.

Yeah, I wouldn't say I've never seen or done that in specific circumstances. but generally no power and ground in the middle layers. and with especially with this Fpga which only needs the one uh, power rail. um which is a yeah 2.8 volts There it is.

Um for the no, Uh, 2.8 volts is for the image sensor. So I think three volt 3.0 it might be running the micro from. This? Is it the same? Yeah, it's the same power. Yeah, yeah yeah, yeah.

it's the same power. And in terms of power distribution, look at this right. Here's our output. I don't know why you'd run it like that and then around like you would just run it straight into there like that.

Okay, you would have. Well, you run it into your cap. Okay, because you the capacitor here. this is your output capacitor.

This is the inductor. Okay, if you switch in regulator, this is your output capacitor. So this becomes your star ground. and then you would have a trace running out there to power this chip.

You'd have a trace running out here to power your image sensor. You'd have a trace running out here to power your microcontroller. You'd have another trace running out here to power your Fpga And you know you might run those on, uh, the bottom layer. But that's only if your electrical, uh, circuit requirements dictated that you have a star grounding, uh sort of thing.

But for something like this, we could just flood fill one the inner layer. The second layer from the bottom would be our you know the entire thing would just be flood filled with our uh, four point our our 2.8 volt rail there. um and then it just drops a via. You know, anywhere it needs to down to the power plane.

So yeah, then you don't have to worry about star grounding. but then you wouldn't run any, uh, tray, any power traces at all down here. you would just stitch it straight down there. Now I could waffle on about all this for ages.

I think I've stopped. I think I've covered sort of most uh, things that I wanted to talk about here. But yeah, you could go in depth down the rabbit hole. Now this design is not that critical.

It's not high speed yes, I know about signal edge rates and all that sort of stuff. But like, it's like the requirements for the performance requirements in terms of layout for something like this. even though it has an Fpga and people say oh, you've got a bypassing requirements and Fpga are ridiculous, No, this is a piss ant little Fpga. It has a single rail.

it has hardly any. you know, power on surge requirements or anything like that. Like, and something like this. Two bypass caps would more than do it.

Um, you could. Anyway, I've done the months in video about how some bypass caps aren't even needed. So yeah, you might get away with one. It depends where the power pins are, if they're like here and here.

Like, you might get away with one bypass cap for your core voltage, your Vcc, and maybe another bypass cap for your I O voltages. uh, for example, and your I O voltages might have been different to your core voltage. For example, you might be running your core voltage at a lower voltage, but in this case, I only got the single 2.8 volts. So the requirements for this night? just one big ground plane.

I wouldn't have any power traces on here at all. Take priority over the critical signals first, and then route your miscellaneous stuff like your I Squared C later and and your uh Jtag interface down here. route all those last and you know things like that and then you wouldn't have to use all these vias all over the place like this. So yeah, shoot for the holy grail of a single-sided layout every time you do an Smd layout.

So anyway, I hope that's um, helped the op there and helped some others with some general advice. I've done lots of videos like this over the years of general like layout advice and stuff like this. but if you like this sort of uh, discussion and like a look at a sort of critique of a design even though this wasn't finished, um, I thought this was just an interesting example, Which you know it brings up a couple of interesting points about layout, so I hope you found it useful if you did, give it a big thumbs up. As always, discuss down below in the comments.

Let me know what you think about the green screen talking Head thing. I think it's better. I think it's better. I know there's some green fringe and if I move quickly you can see the see the green halo and stuff like that.

Lighting in here is not perfect, but I I think the green screen talking head works. I've been doing Youtube professionally for almost 10 years now. It's the first time I've got a green screen. It's got to be some kind of record anyway.

Catch you next time you.