Hi. This video was inspired from a tweet that I got and it was from someone by the awesome name of Johnny Cash I Love us Ferriss tweets now. Fantastic. Absolutely that's a winning name I Love it Johnny Cash None this cash rubbish.

Its cash anyway. Ain't no bet that's been high Ben He's in on the action too. And basically the question yeah started out being I'm seeing a lot of for 8-bit digital computer projects using TTL logic from limited FPGA experience and know that meeting timing is critical for a functioning design. Yet on these simple projects nobody seems to talk about this and talks about signal propagation delay through the wires is much faster than through digital logic and design like this be routed that these constraint without the constraints being violated.

What frequency is this relevant and it talks about that. What could be problematic like routing a clock signal too far away from registers and other things where they have to go through other gates and take other paths on the PCB and it gets complicated. At what point does it become an issue and you'd like someone to clarify this and then ask what's the question? I Guess the question is for simple slow. for 8-bit computers, for example the Gigatron, it is propagation delay for digital signals, an issue in the design, layout and the board, and at what clock frequency roughly would this become a big issue? Well, this opens a rather big can of worms.

It's in some respects fairly easy to clarify in other respects. Well, no, we have to chase a red herring down a rabbit hole yet again. But it's something a lot of people have asked me about over the years and that is what point do I have to start doing these serpentine traces in a design for example to match the length of the traces going to memory and and stuff like that? I Like why and at what point and at what frequency do you do this well I I Kind of replied this in my Tweety it only becomes an issue really at sort of like DD level speeds like you know when you start talking 200 megahertz, couple hundred megahertz, o'clock rates, and stuff like that. Not necessarily, but in generally for high-speed design like this because most people are not going to design their own.

you know, a TTL computer like this. but FPGA Stuff, for example, has timing requirements and there are specific timing analysis tools that you can use inside FPGAs But that's a whole nother. You can do a year's worth of a series of videos on just that issue, but basically on a Ddr or double data rate memory which if you don't know a don't Ddr stands for double data rate and that's when data is actually clocked on both the positive and the negative edge. So twice per clock cycle and the first thing I mentioned in my tweet is the traditional rule of thumb which you must know when you're designing electronics, laying out boards, and stuff like that is the signal propagation through a trace on a PCB is approximately one nanosecond of propagation delay for every 15 centimeters or six inches for you Yanks of PCB trace.

So you've got a trace which goes from here over to here and it's 15 centimeters long. It takes one nanosecond for that signal to travel across your board like that. So if you've got your CPU over here and your memory over here like 15 centimeters away, for example, then it's a 1 nanosecond propagating station. the propagation delay from your CPU to your chip.

but more importantly, and the difference with serpentine traces and trace length matching which is what this video is really going to be about and why you sometimes have to add at what point you really think about having to do this sort of thing is that often you can't route all your traces across. ideally you should. You should prioritize when you're rounding out PCBs You should prioritize high speed memory buses and things like that. But let's just say for the extreme example I put in Twitter here is that if you had one of your signals for example, one of your data pins, take an extra 15 centimeter path to all your other data pins, so that's a real stream example of a really bad constrained PCB layout, but even then, they'd only be a one nanosecond difference.

So if you look at a 100 megahertz DDR memory which clocks on both cycles, so you've got 10 nanoseconds for one cycle. but because it clocks on both the positive and negative edge, it's half that or every 5 nanoseconds, you've got a 1 nanosecond delay in there for your 5 nanosecond, you know, But clocking intervals for your data so that really it starts to become a very significant issue at that point. But that's for a hundred megahertz. but that's for extreme case of 15 centimeters difference between your best case signal and your worst case signal.

But it gets crazy complicated with a design like the Gigatron, which is a TTL computer like this. because, well, okay, there's memory here and there's memory over here, but all these registers and everything else in the actual processor. it's all over the shop. And really, when you're laying out something like this, you wouldn't put any thought into really the layout of this and optimizing it for speed.

You may if you're going after the absolute best possible speed you could for something like this, but generally you wouldn't bother. you, just end up with what you end up with. So when you finish your design, your layout, you build it up and it works. The thing with these sort of computers is you just want them to work right.

You don't care whether it works at, you know, nine megahertz or ten megahertz for example. Not really that important. it's going to work at several Meg's for example, I think the Gigatron I think I've tested it up to about eight megahertz and it works over that. You have to change the chips from seven 4hc on here I Believe other designers of the gigatron have used seven for F-series chips or fast TTL chips which reduces the propagation delay through the actual chip itself are compared to the HD chips.

I Think they've gotten up to. Don't quote me, it's like me, you know, fifteen Meg's or something like that, but really, like nobody cares theory, it is possible to actually simulate this and work out. You know the worst possible propagation delay and at what point it fail in your architecture of your processor and stuff like that. But ah, you wouldn't bother.

Really, that's just no, no, no, no, but it really becomes a big deal on a complex design like something like this. This is a twelve layer open source hardware. I'll link it in our down below. it's some Argentinian thing.

Fantastic. Anyway, it's as I links Kintex A7 fpga with tube ARM Cortex A9 processes in it. It's got 1 gig of Ddr3 memory and if you have a look at here, it's a 12 layer board. It's got the it's Got big Ass processor on here.

Here's your DDR memory. Here's your expansion and look look at all of these serpentine traces. They do this to match the trace links so there's no skew or difference between one data pin, another data pin, or a clock pin. and they you know are another clock pin or something like that.

They even them out not only to memory, but also to this expansion like header up here as well. So you know it and not only between signals, but also between individual pairs. We'll get into that as well. But as I said in my tweet, they're Ddr3 or DDR Level memory is sort of.

Once you start getting into the hundreds of megahertz, this is where it really starts to matter. So anyway, I thought we just do a little dive into some data sheets and stuff like that and just find out exactly why do you have to do this And at what speed does it matter? Wow Let's go into it. but unfortunately, there's some one thing I'm going to leave out of this video and I have to. That will be signal integrity because you'll notice that these these traces down here.

these are thick traces. They are thicker than your other signal layers. signal lines going around here like this. This means that they're obviously doing like a controlled impedance trace because there's a big ground plane underneath here so you can see see that there.

So signal integrity is another thing entirely. even on this which I've done a video on like a removing bypass capacitors. Munson On a board like this doesn't have an effect well on something like this. I DDR Level memory on your computers that you're familiar with.

I'm yeah, it's a big deal. Signal Termination. Signal Integrity. Stuff like that, you'll see termination resistors.

There's different techniques for termination and stuff. Well, oh yeah, if they got termination resistors at the end here and I haven't looked into this design. But anyway, that also factors into the equation of not just propagation delay of signals, but signal integrity as well because then you can get reflections and either like poor. Truly, if you want to analyze this sort of stuff properly, you're going to take signal integrity into account as well.

But today, we're only going to look at signal propagation delay times and setup in whole times and all that sort of jazz. Let's get into it. So this propagation delay a rule of thumb, which I've been talking about. It comes about because a propagation delay on a signal on a bit of copper on a PCB is different than it is through a wire or free air because of the dielectric constant of the PCB material.

What are the fiberglass that it's actually made up with them? You've maybe heard dielectric constant before. a typical Fr4 PCB might be four or four and a half dielectric constant and there's formulas all linking this down below. This is from just Ciara circuits, and there's formulas where you can calculate this sort of stuff and you can even go deeper down into the material science of it and things like that. But basically ER is the dielectric material of constant of the material.

but it basically comes down to here: it is six inches per nanosecond for a typical thing, that's what it is, but it varies between PCBs because the materials vary like standard Fr4, can vary quite significantly in in its dielectric constant and there's better materials. For example: Rogers Corporation make very expensive Very Schmick PCB materials for RF applications another controlled impedance applications. If you're doing a really high-end Ddr4 memory board or something like that where the data rates are phenomenal, you know, high-speed FPGA and all sorts of you know and memory interconnects and architecture and stuff like that, well, you might be using a more controlled impedance piece because something like this. Look, you can choose your dielectric constant from three to ten.

Knock yourself out. Who is this one down here? It's PTF Ceramic dielectric constant three plus minus point. Oh four. thank you very much.

Real expensive exotic materials. You can really do your controlled impedance traces, but you know, for most designers, just a regular Fr4 and just knowing roughly what the dielectric constant is and using the rule of thumb good enough. And if we go into a PCB calculator lot like this certain one which I highly recommend it's the best out there. then we can have a look for a typical trace on top if your PCB like this typical propagation delay, they have it for picoseconds in centimeters and you enter your Er up here your dielectric constant over it.

you know, like a typical four point five for example, and you solve. and it's basically 57.6 picoseconds per centimeter propagation delay. And if you change that to four and it's changing from 57 to 54, even if you go down to extreme three or something like that, you know it's not varying by a huge amount. So if your designs are that critical on your propagation delay to actually work, then even you're working on some bleeding edge system at daylight speeds, or you're just you're doing it wrong.

You're anything. You're being too critical on your design I Constraints You're not being loosey-goosey enough. Yeah, you could come a gutter. and really, you shouldn't on something like this.

you should be operating with reasonably good design margins. We're using a rule of thumb is more than enough and you'll notice. Of course, this doesn't change with frequency. There's 500 megahertz.

Let's drop down to 100. Oh, that doesn't change any, does it? No, it doesn't because it makes absolutely. The frequency doesn't matter, it's the just the propagation delay, the signal. And of course that can change with how your signals route on your piece of.

B As I said, this one is on the top layer with your ground plane underneath like this. Well, that's a micro strip of course and I've actually tweaked my dielectric constantly give a spot on almost spot-on 50 Ohms 50 Ohms I'm thinking impedance up here. No 50 picoseconds per a centimeter here. So let's actually change that to micro strip embedded.

Oh, we've gone up to 55 because it's embedded inside your dielectric material. That's the green part there and in strip line like that. 59. So look it, You know it's gone up fairly significantly.

That's 20% difference right there in your propagation delay just because you've put your signal in there. So if you've got your 12 layer board like this one here, good luck trying to. You can get simulators for this sort of stuff. You know you can do it, field solvers, and like real expensive software to do it.

But look, look at all these. look at all these serpentine squiggly traces in here. So yeah, trying to figure out like exact propagation delays? Of all this sort of stuff, that's why you should be designing with like a rule of thumb with margins kind of thing Like it's it's just yeah. To try and analyze this, you might have to.

As I said, bleeding edge stuff you can hear, maybe okay, knock yourself out, but generally yeah, you shouldn't have to. but be aware that matters, even the weave of the PCB dielectric material. you'll notice like if you have a look at the construction of it, it's weaved like this. You know it's a woven pattern.

And if you run your signal actually on top of one of the weaves and or then like in the direction that it's going in a different dielectric constant than if you do, if it's passing over the ones running in the other direction like that, that can matter as well. That can change your propagation delay right there and your signal integrity and everything else. So let's take a look at a discrete design like this Gigatron. It uses the absolute classic six to 256 SRAM which has been around from date 32k SRAM chip and survival in fast access times from 45 up to 85 nanoseconds.

So let's take the fastest 45 nanoseconds Right off the bat there. you've got the fastest design you could possibly get for your computer. Using this and nothing else considered is about 22.2 megahertz. That's as fast as you can access the memory on this scene.

you can't cycle it any quicker than that. So right off the bat, you know your rule of thumb that 15 centimeters per 1 nanosecond. So right off the bat, if you please excuse the crude of the earth model thing that I'm trying to build and scale water paint it, Um, let's say this is your six two, two, five six chip. Here this is the physical layout of all.

Let's say this is your processor chip over here. I Know the address lines don't match up. You don't actually have to match up the address lines by the way. Little routing trick there you can actually depends on the design.

You can actually it doesn't matter where in this memory you actually store something, depends on the design, But you can actually swap data and address lines because it's just a random array of it. and it's just an array of. it's just a memory array in there. Do you care that it stores it in this part of the thing? No, no, you've got surrounding constraints like this.

So this is what I was talking about before about prioritizing your layout. If you knew that memory speed was important, you wouldn't lack memory on the other side of the processor over here, memory over here, for example, and then a one corner and then you've got across the board and you've got to go. Or we we would've piggledy with your traces and everything else. You wouldn't do it anyway.

But look. this trace here is just by Natural layout is going to be half the length, less than half the length of the one on the outside. Here That could be 30 centimeters. Let's say, it's extreme like that, right? That's only two nanoseconds out of our 45 nanoseconds.

Whoop-dee-doo It's not just the layout of the board is not gonna affect a design like this. Not a chance. That's why computers designers in the 80s really didn't have to take this into account in the general sense they they might have for their like, like nish parts of the design, but overall in the basic scheme of things. No, you just didn't care.

But of course this is where you get up to your setup and hold times and you can get into our way. yeah, that's out of the air, then see our read time in waveforms. Brilliant. If you're doing serious design.

or maybe if you want me to do a video on how to read these kinds of timing diagrams and things like that, please please let me know, because that's an interesting thing. Howdy? What does all the one of these things mean? What is it? What is all this? I Don't get it, You know. Anyway, I'm propagation delay. like for example, the address or the data might have to be on the pins a certain amount of time before the clock pulse comes along and that's called you set up time you died out, or your address.

Your input data to your chip has to be set up before that clock edge it comes along. But in this particular case. ah ah-ha Of course, there's nothing in the read cycle for the set up, but if we go into write address set up time. there you go.

It's actually zero nanosecond, so there is no address requirement, so your data Hester doesn't have to be there. so you've got. Well, let's say that your clock rate was 20 megahertz. For example, you've got a whole 50 nanoseconds to get all of your address signals over there before you clock in that address because there's zero set-up time required.

But depending on how your computer works, your processor, your processor architecture, or your FPGA or whatever it is that you're reading the data, okay, you can. You request your data. For example, it comes out of the chip, but it might be latched into the processor on one of the half cycles for example, opposite clock edge to what you use to get it out of the chip. so you might only have your 25 nanoseconds to get your data across.

and then there might be set-up time on that particular data and things like that. So yeah, you might have to go into that sort of detail. And when you're talking about a TTL computer like this, where the process is actually made up of all these chips, each individual chip, the register in your chip will have its own propagation delay. and as I said, trying to analyze something like that is just nuts.

That's why you wouldn't bother. you'd go mentally insane. You'd have to call the white van and take your way because you just you build it up and you see if it works and then you adjust your clock up and oh look, it works up to ten megahertz purity. but it doesn't work at 11:00 Man, Whatever.

Like if you went in, if you're aside enough you can go in and look at let's go down. have a look at the propagation delays. here. they are.

You just scroll down until you see the nanoseconds is 12 nanoseconds. That's typical, but that's gonna vary with voltage with temperature with all sorts of stuff. So there you go. I Like you know right there.

you combine that with all the other dozens and dozens and dozens of chips on here. But as I said, you could use a faster logic seven for F for example. It's gonna have a faster propagation delay time than this. So yeah, you might be able to eke out a more speed and more speed from users not designed by doing that.

But generally, yeah, you're going to be constrained in these TTL type designs drastically. All right, let's take a quick look at DDR Memory. as I said on this Xilinx processor board that which uses Ddr3 memory. Now, this won't be a DDR 3 tutorial because no, that's a one-hour video in its own right and this will just have a quick look at the datasheet years.

So here's our termination resistors over here. 40.2 aims. They go to a specific midpoint termination voltage and our way going to the reasons why. It's a complex issue If you really want to get into termination of DDR memory and all that sort of jazz anyway, you don't pull them high and I pull them low.

it's it's a to a voltage series voltage source anyway. yet this is the meri chip that we're using Ddr3 so let's here we go. it's a micron job' and it's you know it's pretty new tech. Let's let's take a look at this thing.

These are our cycle times down here. Look at this. 938 picoseconds. We're talking puffs here.

I'm this nanosecond rubbish, right? for the Ddr3 2133. Not sure what value we have on this design, but we're down into the 1 nanosecond class time in here right then. This is just cycle little in propagation delay and skew between signals. You hear me start talking more about skew rather than propagation delay at this point, because what we start talking about now is a difference between one signal and another.

So the skew between the signals. You want everything to be clocked all at the same time you want. Or if you send out an address from your processor to your memory chip, you want them all all the pins to arrive there at the same time. That's why you want a length match.

and when you're down in cycle times like one nanosecond, it's really gonna matter. And these data sheets have 200 plus pages for a reason. I Can't possibly go into all the details of driving DDR Memory I mean just the state diagrams enough to scare you away. Well, as always with these videos I didn't actually plan before I went ahead with this I just press record and see what happens and I started going through the datasheet and I'm just like my eyes are rolling.

How do I increase the signal-to-noise ratio here and pull out the important stuff? So I went and I looked bugger it micron have probably got an app note that will make it a bit easy, a little bit easier for us anyway and sure enough they do. I'll link it in down below point to point simulation process and this talks about your time in budget which is a big thing that you'll hear in these types of designs. When you're like, you wouldn't always do this if you're laying out this board here right like you wouldn't I would not go in and do a timing budget for something like this I just really wouldn't like waste my time and do enough. Sometimes there's not a waste of time, but I really wouldn't bother all I would know, is that right? Let's just match the lengths of the traces and that's it.

and and just be done with it, right? You don't have to worry about stuff like like how how close do I need to match, just match him to within nine like half Abby's dick. you know, five millimeters or something like that set some constraint in there. match all of the lines to the DDI together and then and then you don't have to worry about doing the sorts of stuff which we're about to take a look at here looking at analyzing era budgets. There's a clock sauce, there's a transmitter which might be your processor slash FPGA for example, there's data and strobe lines, and there's receiver and these all have skew or propagation delay.

Just think of skew and propagation delay is the they're effectively the same thing. You've got the transmitter skew. here, you've got the PCB skew, which is the thing we're interested in, and the receiver skew as well like the internal set up and hold propagation delay times inside the chip and the transmitter as well when it's sending data back. So then they talk about the signal integrity process.

As I said, we won't talk about signal integrity, but it does impact these things. So anyway, in this particular case, they've got a two hundred and sixty six megahertz period, which is a 3.75 nanosecond half period. Because it's it's DDR double data rate. So we've got a set-up budget of 1.8 nano at one point.

eight seventy five nanoseconds. Because we're working 18 hundred picoseconds. We're now down into the picosecond region here, right? This is this is real engineering. And then we've got our hold budget of 1875.

And then they've They've pulled out the transmitter skew. Well, they tell you where they get it from the vendor datasheet here, and then they tell you that, what budget do we have left over? We have five hundred and 85 picoseconds for our PCB skew. So that's the longest period that we can afford. The biggest mismatch we can afford to have between the traces on our PCB and it'll might tell you which trace as we go down into, but basically set up and hold times are exactly the same.

So right off the bat we get our confusing here. and so 150 millimeters, none of that inches, rubbish, 150 millimetres times 0.5 85 because it's a nano per nanosecond so we're talking add up to 87 millimeters 87 millimeters difference that we can have maximum difference between. Let's just say, all of our tracers. We don't know exactly which ones yet, but you know, let's just keep it simple.

So there you go, up to 85 and that 87. That sounds like a lot and we won't mention voltage, margin, and stuff like that. Let's just let's just not go there. This is an interesting diagram.

It shows the skew and how the the data is only valid with inside. here. If your skew let's say your skew was this big here, then it would start impacting into this squeeze in that the eye Narrows It's called the eye and it narrows and narrows and narrows until well, you're operating a valid window for your data is Nephal and then your system just completely falls over. And the reason we don't go into our signal integrity or speak as well.

yeah, just gets a bit complicated. Done it. But aha, the board skew budget. We have to actually break that down even further.

it gets more complicated the components that make up the board skew budget. include is a V ref noise path length mismatch which is that main thing that we're talking about crosstalk input capacitance, mismatch termination resistor tolerance a type of termination where the termination resistors are nuts so we can look at the different components here and they break them down which is really good. First of all, we've got the ISI which is our inter symbol interference. What that basically means is a symbol is is what's inside the I here right? The the type of data that you've got in there and due to reflections on your PCB you might have one data interfering the previous data interfering with the new data because then you've got some overshoot undershoot, some reflections coming back and that can interfere sometimes sometimes not.

It doesn't always happen because your data is always changing, so some symbols some combination of data may interfere with another combination of data if they're in the right order, depend on termination. so I'd like it's it's to do with the data that you're actually transferring, not just the fact that you've got your termination right Anyway, inter symbol interference and and that sort of tells you it can cause by the bus running faster than it can settle basically because you need time for at or before you send the next data so that your data doesn't interfere with from the previous data due to signal integrity issues. So anyway that is a component of that and then you've got crosstalk between your signals because your signals are right next to each other and there they're talking and they're coupling. and if you're routing them, they're typically running parallel like that.

And when you have tracers running parallel like that with no ground shield in between them, you get capacitive coupling. If trace is just crossed like that, the cross talks very little because there's little mutual capacitance between them. But when you're running buses like this all the way up, then the crosstalk can be very serious and we won't go into differential mode common mode and we get in a signal Integrity Come on, and coupled circuits is all just part of that. We won't talk about crosstalk effects, blah blah blah IV ref annoys.

That's a thing. As I said, the termination The vote is terminated to a mid rail voltage reference. You can actually get specific foliage reference DDR termination chips that are actually designed to do this and the noise of these reference voltages impacts your budget. Fit your timing budget for the amount of skew that you can have on your PC be the difference in your traces.

So for example, with a point 5 volt per second edge rate and a 50 millivolt V RF noise and it's two hundred picoseconds of strobe to data skew and there you go. It's extremely important aspect of Ddr Sdram design. When laying out, the trace should be as wide as possible to reduce inductance on the line. So really, here's with Sigmund: Tegrity does matter just on getting your voltage reference.

and I've done DDR designs where I've decoupled and inductor isolated the V ref to buggery because it matters and then they tell you about the space into adjacent signals from the V ref because you typically want to keep your V ref isolated from crosstalk from other signals as well. So not only crosstalk between signals, but crosstalk between your signals and your voltage reference for you Termination resistance. and this has a large impact on your total time in budget. Here, we were just going to talk about like propagation delay of traces.

No, it's more than that. Then you've got input capacitance variation. Look at your data sheet. We could go in and see what our input capacitance variation is.

Should we do that? Yeah, why not look at all this. ODT sensitivity definition to do with the I/o calibration. Oh ha, I found it. You search for capacitance and Bob's your uncle.

This input output capacitance tada. But look at this. The variation 1.4 to 2.5 I can ruin someone's day and someone could be you. And would you like single-ended or differential fries with that sir? So anyway, yeah, that could matter.

Let's get down here. here. we go. Here's our time in budget.

Okay, so this is you. Remember this was a transmitter security, the receivers cue, and all of this stuff down here is the stuff that's made up is our budget for our total PCB SKU basically. but if you have a look here, the path length mismatch. That's all we got.

That's all we got. calculation from spec When you subtract all the other stuff from the total. what was it? The 580 or whatever picoseconds that we had When you take out crosstalk and and intersymbol interference and V ref noise? it doesn't leave you much budget. 30 picoseconds So yeah, what's that? Get the confuse out again.

So average PCB at. you know the our rule of thumb: 150 millimetres times point I do five if the picoseconds we're talking seven point five millimeters. There you go. So seven point five millimeters just just off the bat.

there is kind of like the worst case we could get if we were using the laying out this board with this chip. and that would include that you know the PCB We've problems variation in the dielectric constant of the PCB material. stuff like that right? that we're not including any of that. So right off the bat there seven and a half.

So good design. Prudence would say you would at least have that to be on the safe side. So you know, as I said like you'd be down in the millimeters before I Kind of guessed you know I said less than like five millimeters difference. There you go.

that's why, Because right? So you'd say oh like a couple of millimeters difference. For example, because when you're laying out this kind of PCB you can do it. I've done it without the the tools to automatically drag and do the you know when you drag your Eve your differential pair or your single pair to match the lengths I've done it without the automated tools to do that. But when you have a PCB tool and I believe Kicad.

although I haven't actually used it, believe Kicad actually does have route here. it is tuned track length, tune, differential pair length, and things like that I haven't used it Anyway, we can somehow tune that and we can set the parameters and things like that too. Haven't used this in Kicad, so please forgive me. But anyway, when you've got an automated tool to do it, you may as well sit fairly precise.

Constraint: Yeah, there's no reason why it can't be within a millimeter or two something like that, so you wouldn't go. Oh, I've got seven and a half millimeters to play with because I Calculated my timing budget I'm a hero and I spent a whole week working on my timing budget. No, just just lay out your board so that you've got no skew between the signals there match to within a millimeter or two. So anyway, that is why you see all of these little zigzaggy serpentine traces like this on boards is because they're trying to match the links in this case, which is what's this signal there? There you go Yet this is DDR So this is actually a differential pair.

Okay, so this is a the positive and negative. You can see it a DQ S3 negative and positive. So they're actually so. This is why you're keeping the pairs going like that and this one is a good example.

It just happens to be a good example because look, not only do you have to match the length of this pair here to data pair for and five and six and seven, you match those links. between the pairs, you also match the difference. This is why it's got an extra little kink in here. Look at this little kink going out here like this and the other one doesn't have it because you're matching the difference between d3 positive and negative.

So you match the length there and you're taught your automated tool can actually do this and you can do it manually. I've done lots of boards where I've had to manually add in the squiggles and it's a lot more work. So why these tools are valuable in a PCB when you're laying out DDR memory is it can save you a lot of time. Can do the push and shove and it does.

You just set it up, you know I Want this maximum difference between your pairs like this so it'll add in these little kinks. There's another little kink out here as well. you can see that and and then it'll also match those between the pair's as well when you when you manually lay in them out or if your auto routing. But anyway, that's why you have these two different types of serpentine traces like this.

both within a differential pair and between differential pairs or between single ended traces like d0 to d7 and a zero to a seven or whatever it is on your memory. So that's it. There you go. So yeah, this video is long enough.

sorry, but that's basically what it comes down to is timing. Budgets and timing. Budgets are critical. But as I said, you don't have to go in and do a timing budget.

you laying out a board with your DDR memory or whatever. You know it's critical because I've told you so. Everyone's told you so Mike runs told you so every Tom, Dick and Harry's told you so and you can go in and analyze it yourself. but you don't have to.

If I was laying out this board as I said, I would just set those constraints to a millimeter or something like that. Something reasonable. Don't set it to like 0.01 millimeters half Abby's deep because the software is just going to go. do it.

Sorry, Yeah, it's don't gild the lily there, but that's what you have to do. Just do that. It's critical, put it in, and then you've got other signal integrity things to worry about. In fact, it might tell you that.

Yep, it does. There you go, they talk about split return paths a bit here, so if you've got, you, never split your ground planes. If you add a little cut out in your ground plane like that, not a physical cut out, route it out part of your board. But if you for some reason didn't flood, fill your ground under there and it's gonna take a longer path.

Oh, you've just ruined your day right there. Again, you've ruined your timing budget. You've really just signal integrity. You ruined everything and well, yeah, they're gonna suck your ass because she didn't know how to lay our boards.

So there you go. I hope you liked that video. can't as I said, can do video whole video series of just on signal integrity, just on doing analyzing DVR timing, budgets and and things like that anyway I hope you learned something from the video. If you did, please give it a big thumbs up.

And if you want to see more videos of you know more specific stuff like this then please let me know. and occasionally I'll see a tweet like that and it just goes. Oh yeah, I'll do a video on that I'll just press record and have a read for half an hour anyway. I Hope you liked it as always discuss down below in the comments or over on the EEV blog forum.

Catch you next time.